J
Jan Decaluwe
If you are doing HDL-based design, you are probably using
integer arithmetic regularly. In doing so, you may often be
struggling with mysterious behaviour, sign bit extensions,
resizings and type conversions, in order to get things
to work as you want.
I believe such efforts are a waste of your valuable
engineering time, caused by bad language design choices
in Verilog and VHDL.
I have written an essay that explores these issues in
detail, and proposes a solution:
http://www.jandecaluwe.com/hdldesign/counting.html
integer arithmetic regularly. In doing so, you may often be
struggling with mysterious behaviour, sign bit extensions,
resizings and type conversions, in order to get things
to work as you want.
I believe such efforts are a waste of your valuable
engineering time, caused by bad language design choices
in Verilog and VHDL.
I have written an essay that explores these issues in
detail, and proposes a solution:
http://www.jandecaluwe.com/hdldesign/counting.html