Integer Division

Discussion in 'VHDL' started by Bliss, Feb 26, 2008.

  1. Bliss

    Bliss Guest

    I am a complete novice to this language. Although I searched a lot for
    division of integers in VHDL I couldn't find much. The previous posts
    in this group were helpful but since I don't know much at this stage I
    couldn't get them fully. Please guide me and suggest some sites which
    can provide algorithms and related text regarding integer division.

    Another query - does the / sign work in VHDL?
     
    Bliss, Feb 26, 2008
    #1
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  2. "/" works if you have defined a procedure or loaded the appropriate IEEE
    library.


    As for division
    http://courses.cs.vt.edu/~cs1104/BuildingBlocks/divide.030.html

    "binary" "division" "algorithm " "RTL" turns up some interesting hits on
    google.

    Were you planing to divide by a constant, a constant power of 2, or some
    variable value?
    Each can be optimized and instituted differently.

    "Bliss" <> wrote in message
    news:...
    >I am a complete novice to this language. Although I searched a lot for
    > division of integers in VHDL I couldn't find much. The previous posts
    > in this group were helpful but since I don't know much at this stage I
    > couldn't get them fully. Please guide me and suggest some sites which
    > can provide algorithms and related text regarding integer division.
    >
    > Another query - does the / sign work in VHDL?
     
    Dwayne Dilbeck, Feb 26, 2008
    #2
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  3. Bliss

    Duane Clark Guest

    Bliss wrote:
    > I am a complete novice to this language. Although I searched a lot for
    > division of integers in VHDL I couldn't find much. The previous posts
    > in this group were helpful but since I don't know much at this stage I
    > couldn't get them fully. Please guide me and suggest some sites which
    > can provide algorithms and related text regarding integer division.


    Integer division by its very nature requires a lot of logic to
    implement. Therefore, doing an integer division requires that you
    balance the factors of:
    Required resolution
    Required latency time/clocks
    Required division time/clocks
    Resource utilization

    The solution you pick is going to depend on how you balance those factors.

    >
    > Another query - does the / sign work in VHDL?


    In simulation, yes. But generally not in synthesis, because the
    synthesis tool does not know how to balance your design requirements.
     
    Duane Clark, Feb 26, 2008
    #3
  4. Bliss

    KJ Guest

    >> Another query - does the / sign work in VHDL?
    >
    > In simulation, yes. But generally not in synthesis, because the synthesis
    > tool does not know how to balance your design requirements.


    Synthesis sure does support division (depending on the tool). Try
    implementing a<= b / c with Quartus and it will synthesize just fine. You
    make not like the performance because it is a hunk-o-logic but when you say
    you want "a<= b / c" that combinatorially implements that logic that you
    requested.

    Kevin Jennings
     
    KJ, Feb 27, 2008
    #4
  5. Bliss

    Duane Clark Guest

    KJ wrote:
    >>> Another query - does the / sign work in VHDL?

    >> In simulation, yes. But generally not in synthesis, because the synthesis
    >> tool does not know how to balance your design requirements.

    >
    > Synthesis sure does support division (depending on the tool). Try
    > implementing a<= b / c with Quartus and it will synthesize just fine. You
    > make not like the performance because it is a hunk-o-logic but when you say
    > you want "a<= b / c" that combinatorially implements that logic that you
    > requested.


    Hmm.. a combinatorial implementation. A somewhat scary thought ;) But
    yea, I could see synthesis tools supporting division, especially if it
    would support absorbing registers following the division into a pipeline
    (something like XST does already with multipliers). That would be a
    useful feature.
     
    Duane Clark, Feb 27, 2008
    #5
  6. Duane Clark wrote:
    > In simulation, yes. But generally not in synthesis, because the
    > synthesis tool does not know how to balance your design requirements.


    Xilinx ISE 9.2 does synthesize it - if the divisor is a constant and a
    power of 2, that is. It is synthesized as a shift then.

    - Philip
    --
    When all questions of space, time, matter and the
    nature of being have been resolved, only one question
    remains - "Where shall we have dinner?"
    (Douglas Adams)
     
    Philip Herzog, Feb 27, 2008
    #6
  7. Bliss

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Check this page: Division

    This gives a more interactive presentation of division: Opar1
    Jeppe
     
    jeppe, Mar 10, 2008
    #7
  8. Bliss

    Bliss Guest

    On Feb 27, 4:36 am, "Dwayne Dilbeck" <> wrote:
    > "/" works if you have defined a procedure or loaded the appropriate IEEE
    > library.
    >
    > As for divisionhttp://courses.cs.vt.edu/~cs1104/BuildingBlocks/divide.030.html
    >
    > "binary" "division" "algorithm " "RTL" turns up some interesting hits on
    > google.
    >
    > Were you planing to divide by a constant, a constant power of 2, or some
    > variable value?
    > Each can be optimized and instituted differently.
    >
    > "Bliss" <> wrote in message
    >
    > news:...
    >
    > >I am a complete novice to this language. Although I searched a lot for
    > > division of integers in VHDL I couldn't find much. The previous posts
    > > in this group were helpful but since I don't know much at this stage I
    > > couldn't get them fully. Please guide me and suggest some sites which
    > > can provide algorithms and related text regarding integer division.

    >
    > > Another query - does the / sign work in VHDL?


    Thanks for replies. The binary division link was of great help.
    Actually I don't need a hefty and precise code for the division, just
    a simple and approx. one. It's a small part of our big final year
    project. So, at the Under grad level a not so accurate code would do.
     
    Bliss, Apr 15, 2008
    #8
  9. Bliss

    Dal Guest

    On Feb 27, 7:05 am, Bliss <> wrote:
    > I am a complete novice to this language. Although I searched a lot for
    > division of integers in VHDL I couldn't find much. The previous posts
    > in this group were helpful but since I don't know much at this stage I
    > couldn't get them fully. Please guide me and suggest some sites which
    > can provide algorithms and related text regarding integer division.
    >
    > Another query - does the / sign work in VHDL?


    Note if by simple you mean your dividend or divisor is constant and/or
    your integers have a small range it may be efficient to implement the
    divide as a look up table.
     
    Dal, Apr 15, 2008
    #9
  10. Bliss

    Bliss Guest

    On Apr 15, 5:02 pm, Dal <> wrote:
    > On Feb 27, 7:05 am, Bliss <> wrote:
    >
    > > I am a complete novice to this language. Although I searched a lot for
    > > division of integers in VHDL I couldn't find much. The previous posts
    > > in this group were helpful but since I don't know much at this stage I
    > > couldn't get them fully. Please guide me and suggest some sites which
    > > can provide algorithms and related text regarding integer division.

    >
    > > Another query - does the / sign work in VHDL?

    >
    > Note if by simple you mean your dividend or divisor is constant and/or
    > your integers have a small range it may be efficient to implement the
    > divide as a look up table.


    No they are variables. By simple I mean that I can compromise on
    accuracy and the result needn't be a floating point no.
     
    Bliss, Apr 15, 2008
    #10
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