Integer left shift operation

Discussion in 'VHDL' started by cltsaig, Oct 7, 2004.

  1. cltsaig

    cltsaig Guest

    Hi all,

    I got an syntax error with the following left shfit operation assignment.
    # Assignment target incompatible with right side. Expected type
    "INTEGER".
    # Cannot find function to_integer for these actuals.
    # Undefined type of expression.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.al

    process
    variable ip1, nprev: integer;
    begin
    nprev:=20;
    ip1:=to_integer(to_StdLogicVector(nprev) sll 1);
    end process;

    Any help will be very appreciate!!!

    Kindest regards,
    Stanley
     
    cltsaig, Oct 7, 2004
    #1
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  2. cltsaig a écrit:
    > Hi all,
    >
    > I got an syntax error with the following left shfit operation assignment.
    > # Assignment target incompatible with right side. Expected type
    > "INTEGER".
    > # Cannot find function to_integer for these actuals.
    > # Undefined type of expression.
    >

    [...]
    > ip1:=to_integer(to_StdLogicVector(nprev) sll 1);
    > end process;
    >
    > Any help will be very appreciate!!!


    You don't use sll with the right syntax:
    ip1:=to_integer(sll(to_StdLogicVector(nprev),1));

    but I'm not sure this will work. IIRC, sll can only be used with
    bit_vector type.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Oct 7, 2004
    #2
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  3. cltsaig

    Alan Fitch Guest

    "cltsaig" <> wrote in message
    news:...
    > Hi all,
    >
    > I got an syntax error with the following left shfit operation

    assignment.
    > # Assignment target incompatible with right side. Expected type
    > "INTEGER".
    > # Cannot find function to_integer for these actuals.
    > # Undefined type of expression.
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    > use ieee.math_real.al
    >
    > process
    > variable ip1, nprev: integer;
    > begin
    > nprev:=20;
    > ip1:=to_integer(to_StdLogicVector(nprev) sll 1);
    > end process;
    >
    > Any help will be very appreciate!!!
    >


    In Numeric_std, sll is defined for types signed and unsigned.
    So you need to do

    a) convert your integer to unsigned
    b) shift left, producing an unsigned result
    c) convert from unsigned back to integer

    ip1 := to_integer( to_unsigned(nprev, 5) sll 1 );

    Note that to_unsigned takes a second argument specifying the
    width of the resultant vector.

    Regarding the problem, you could of course with your
    example code simply say

    ip1 := 40; -- only joking! :)

    It might be worth trying (depending on your synthesis tool)

    ip1 := nprev * 2;

    as multiplication by a constant power of 2 is understood
    by many tools and can be implemented by a shift in hardware.

    If you want to use integers, and they are for representing
    unsigned values, I would declare them as "natural" rather than
    "integer".

    You may find that if you are doing lots of bit shifting
    and arithmetic operations, it is easier to use the vector
    types unsigned and signed, and then convert the final output
    to the required type.

    regards
    Alan


    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
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    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Oct 7, 2004
    #3
  4. cltsaig

    cltsaig Guest

    Hi Alan and all,

    Greatly thanks for your supports and I'll try the way you just told me!!

    Many thanks!!!

    BR,
    Stanley
     
    cltsaig, Oct 7, 2004
    #4
  5. cltsaig

    rickman Guest

    cltsaig wrote:
    >
    > Hi all,
    >
    > I got an syntax error with the following left shfit operation assignment.
    > # Assignment target incompatible with right side. Expected type
    > "INTEGER".
    > # Cannot find function to_integer for these actuals.
    > # Undefined type of expression.
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    > use ieee.math_real.al
    >
    > process
    > variable ip1, nprev: integer;
    > begin
    > nprev:=20;
    > ip1:=to_integer(to_StdLogicVector(nprev) sll 1);
    > end process;


    Doesn't to_StdLogicVector() require TWO prameters? I think you need to
    define the width of the vector.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 7, 2004
    #5
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