Integer or STD_LOGIC_VECTOR

Discussion in 'VHDL' started by jk, Jan 13, 2004.

  1. jk

    jk Guest

    Hi,

    I am sort of new to VHDL and still trying to get around the optimisation
    considerations associated with the language as opposed to using C.

    A have written a function which uses a variable 'ppos' to hold the current
    position in a vector. I have defined it as an INTEGER but I am beginning to
    think that it might be more efficient implemented in binary. Is this a real
    consideration in VHDL coding? Would using a binary vector in place of an
    integer wherever possible resort in a more efficient implementation in the
    long run?

    cheers

    - Kingsley
    jk, Jan 13, 2004
    #1
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  2. jk a écrit:
    > Hi,
    >
    > I am sort of new to VHDL and still trying to get around the optimisation
    > considerations associated with the language as opposed to using C.
    >
    > A have written a function which uses a variable 'ppos' to hold the current
    > position in a vector. I have defined it as an INTEGER but I am beginning to
    > think that it might be more efficient implemented in binary. Is this a real
    > consideration in VHDL coding? Would using a binary vector in place of an
    > integer wherever possible resort in a more efficient implementation in the
    > long run?


    Hi
    Integers always end up synthesized to binary numbers so you don't have
    much to worry about that. The only way you can improve the synthesis
    efficiency is to limit the possible values of your integer.
    Since "ppos" represents a position in a vector, it is a positive
    integer, a.k.a. natural. Your vector is not of infinite length, I don't
    think it is longer than 128 bits (which is already quite long) so you
    can define ppos like this:
    signal ppos : natural range 0 to 127;
    This way you tell the synthesizer that it won't need more than 7 bits to
    represent ppos.


    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Jan 13, 2004
    #2
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  3. jk

    Kwaj Guest

    Nicholas,

    beautiful response - it was exactly what I was looking for given my
    unfamiliarity with the language. thanks a lot

    - Kwaj


    "Nicolas Matringe" <> wrote in message
    news:...
    > jk a écrit:
    > > Hi,
    > >
    > > I am sort of new to VHDL and still trying to get around the optimisation
    > > considerations associated with the language as opposed to using C.
    > >
    > > A have written a function which uses a variable 'ppos' to hold the

    current
    > > position in a vector. I have defined it as an INTEGER but I am beginning

    to
    > > think that it might be more efficient implemented in binary. Is this a

    real
    > > consideration in VHDL coding? Would using a binary vector in place of an
    > > integer wherever possible resort in a more efficient implementation in

    the
    > > long run?

    >
    > Hi
    > Integers always end up synthesized to binary numbers so you don't have
    > much to worry about that. The only way you can improve the synthesis
    > efficiency is to limit the possible values of your integer.
    > Since "ppos" represents a position in a vector, it is a positive
    > integer, a.k.a. natural. Your vector is not of infinite length, I don't
    > think it is longer than 128 bits (which is already quite long) so you
    > can define ppos like this:
    > signal ppos : natural range 0 to 127;
    > This way you tell the synthesizer that it won't need more than 7 bits to
    > represent ppos.
    >
    >
    > --
    > ____ _ __ ___
    > | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    > | | | | | (_| |_| | Invalid return address: remove the -
    > |_| |_|_|\__|\___/
    >
    Kwaj, Jan 13, 2004
    #3
  4. Please DONT forget to use RANGE casting of your integer.

    Please goto http://www.amontec.com/fix/vhdl_memo/index.html to know the
    how to use RANGE VHDL keyword.

    ex : If you do not use range for a 4 bits counter based on integer
    signal, you will synthesize 'in reality' a 32 bits counter -> too many
    flip-flops and a very bad speed of your 4 bits counter.

    So, we ( Amontec Team ) never use integer for RTL description, but we
    use unsigned type (look lib ieee.std_numeric.all).

    Also, do not use std_logic_vector but std_ulogic_vector.

    Laurent
    www.amontec.com

    If you are describing RTL synthesizable VHDL code

    Nicolas Matringe wrote:

    > jk a écrit:
    >
    >> Hi,
    >>
    >> I am sort of new to VHDL and still trying to get around the optimisation
    >> considerations associated with the language as opposed to using C.
    >>
    >> A have written a function which uses a variable 'ppos' to hold the
    >> current
    >> position in a vector. I have defined it as an INTEGER but I am
    >> beginning to
    >> think that it might be more efficient implemented in binary. Is this a
    >> real
    >> consideration in VHDL coding? Would using a binary vector in place of an
    >> integer wherever possible resort in a more efficient implementation in
    >> the
    >> long run?

    >
    >
    > Hi
    > Integers always end up synthesized to binary numbers so you don't have
    > much to worry about that. The only way you can improve the synthesis
    > efficiency is to limit the possible values of your integer.
    > Since "ppos" represents a position in a vector, it is a positive
    > integer, a.k.a. natural. Your vector is not of infinite length, I don't
    > think it is longer than 128 bits (which is already quite long) so you
    > can define ppos like this:
    > signal ppos : natural range 0 to 127;
    > This way you tell the synthesizer that it won't need more than 7 bits to
    > represent ppos.
    >
    >
    Amontec Team, Laurent Gauch, Jan 14, 2004
    #4
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