integer to std_logic_vector if width not known apriori?

[JimG]

In the case of attempting to write reusable code for a watchdog timer, can an integer be converted to a std_logic_vector without providing the desired width?

I have a generic counter function; I'd like to define only the timeout value and clock frequency and have the appropriate counter parameters be calculated.
So,
timeout / (1/freq) = real
real => integer
integer => std_logic_vector (of calculated width)

... escentually this would be a 'RANGE on an integer

This seems a very common need but isn't covered in the VDHL guides I have.

Thanks for any available help.