Inverted Clock in ACEX1K

Discussion in 'VHDL' started by Manfred Balik, Aug 29, 2003.

  1. Hello all,

    I'm using an Altera ACEX1K and I want to invert my incoming clock and use
    this clock outside the FPGA.
    But I can't do anything with the incoming clock, if I use altclklock to use
    the intern clock-network.
    Please, can someone help me.

    Thanks, Manfred
    Manfred Balik, Aug 29, 2003
    #1
    1. Advertising

  2. If you use altclklock, you cannot invert or run the clock to any gate.
    Your choices seem to be to not use altclklock on the GCLK pin or use the
    other dedicated clock pin (which does not have a PLL).

    Manfred Balik wrote:
    > Hello all,
    >
    > I'm using an Altera ACEX1K and I want to invert my incoming clock and use
    > this clock outside the FPGA.
    > But I can't do anything with the incoming clock, if I use altclklock to use
    > the intern clock-network.
    > Please, can someone help me.
    >
    > Thanks, Manfred
    >
    >


    --


    Marc Guardiani

    To reply directly to me, use the address given below. The domain name is
    phonetic.
    fpgaee81-at-eff-why-eye-dot-net
    Marc Guardiani, Aug 30, 2003
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Valentin Tihomirov

    Are clock and divided clock synchronous?

    Valentin Tihomirov, Oct 23, 2003, in forum: VHDL
    Replies:
    11
    Views:
    3,285
    louis lin
    Oct 28, 2003
  2. Replies:
    4
    Views:
    716
    Peter Alfke
    Apr 27, 2006
  3. Replies:
    5
    Views:
    2,159
    Ricardo
    Jun 23, 2006
  4. AviraM
    Replies:
    2
    Views:
    6,366
    Manish Pandit
    Sep 28, 2006
  5. himassk
    Replies:
    1
    Views:
    1,230
    Paul Uiterlinden
    May 16, 2007
Loading...

Share This Page