Inverter Chain Synthesis Problem

Discussion in 'VHDL' started by Davy, Dec 16, 2005.

  1. Davy

    Davy Guest

    Hi,

    I work on Xilinx ISE, and my synthesis tool is XST and synplify.
    I use verilog to write a Inverter Chain (delay ) like out =
    ~(~(~(~...in)).
    But the circuit be synthesised cancel all the invorter.

    How to synthesis out all the inverter chain I want?

    Any suggestions will be appreciated!
    Best regards,
    Davy
    Davy, Dec 16, 2005
    #1
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  2. Davy wrote:

    > How to synthesis out all the inverter chain I want?
    > Any suggestions will be appreciated!


    I would use a counter or shifter
    to generate the delay.

    -- Mike Treseler
    Mike Treseler, Dec 16, 2005
    #2
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  3. Davy

    Davy Guest

    Hi Mike,

    I mean a comb logic delay.

    Davy
    Davy, Dec 16, 2005
    #3
  4. Davy

    John_H Guest

    Davy wrote:
    > Hi Mike,
    >
    > I mean a comb logic delay.
    >
    > Davy


    A combinatorial chain of inverters is probably a bad idea. The timing
    isn't easily guaranteed within a tight range especially since routing
    isn't constrained to specific paths. If you *must* try to keep the
    inverters, synplify would use the syn_keep attribute on the
    combinatorial elements you don't want removed. Even then, you may need
    similar constraints in place & route.

    Please don't go there.
    John_H, Dec 16, 2005
    #4
  5. Davy

    keyrun Guest

    actually whaen u r generating a netlist if u r using series of
    inverters but using only first input and the final output the synthesis
    tool will won't consider and it will think as redundant terms during
    translation phase ............... i think it's easy to use a counter to
    generate delay .............if there is any ways of generating delay
    just let me know
    keyrun, Dec 16, 2005
    #5
  6. Davy

    Davy Guest

    Hi,

    Thank you for your help :)

    Do you think what's the best way to generate delay smaller than a clock
    period?

    Best regards,
    Davy
    Davy, Dec 16, 2005
    #6
  7. Davy

    backhus Guest

    Davy schrieb:
    > Hi,
    >
    > Thank you for your help :)
    >
    > Do you think what's the best way to generate delay smaller than a clock
    > period?
    >
    > Best regards,
    > Davy
    >

    Hi Davy,
    unfortunately you didn't tell why you want to create such a delay.
    That would help to give you useful help.

    One solution may be to feed the signal into a DFF that is clocked by the
    falling edge of your clock signal (assuming that the rest of your
    circuit uses the rising edge). Thus you get a delay of half a clock period.

    Another way could be constraints. While max_delay constraints are
    available I'm not sure about min_delay constraints.

    The problem with combinatorical delays in FPGAs is that they are
    somewhat meaningless, since the routing delays between the LUTs are much
    higher and (unless propperly constrained) not predictable. So this
    approach is probably the worst choice, sice it is wasting LUTs for no
    reason.

    Have a nice synthesis

    Eilert
    backhus, Dec 16, 2005
    #7
  8. Davy

    John_H Guest

    Davy wrote:
    > Hi,
    >
    > Thank you for your help :)
    >
    > Do you think what's the best way to generate delay smaller than a clock
    > period?
    >
    > Best regards,
    > Davy


    If you have a steady clock in the right frequency range for your device,
    you can use a PLL, DLL, or DCM to get a different delay than 1.0 or 0.5
    clock periods.

    The DCM especially allows you to set up a shifted clock with 1/256th of
    a clock resolution (or about 50 ps, whichever is greater) of delay.
    This precisely delayed clock can give you the precision control over
    skew that today's designers need.

    If you're in Virtex-4 devices, the inputs have per-pin controllable
    delays that are calibrated to give you 78 ps delay resolution on
    unclocked signals.

    So - is your device able to supply the fun stuff? More application
    details can bring out the info on the "best" feature set to use.
    John_H, Dec 16, 2005
    #8
  9. Davy

    Jason Zheng Guest

    Davy wrote:
    > Hi,
    >
    > I work on Xilinx ISE, and my synthesis tool is XST and synplify.
    > I use verilog to write a Inverter Chain (delay ) like out =
    > ~(~(~(~...in)).
    > But the circuit be synthesised cancel all the invorter.
    >
    > How to synthesis out all the inverter chain I want?
    >
    > Any suggestions will be appreciated!
    > Best regards,
    > Davy
    >


    For synplify tools,

    wire [3:0] inv_chain/*synthesis syn_keep=1*/;

    assign inv_chain[3:0] = ~{inv_chain[2:0], din};
    assign dout = inv_chain[3];

    I'm not use what XST uses in equivalence to syn_keep. It might be the same.

    Like other ppl pointed out, you shouldn't expect to use invertor chains
    for any precision timing control. There are just too many uncertainties
    in FPGA. But if you just want to insert some combinational delay to
    solve some racing conditions, it might come in handy.

    cheers,

    jz
    Jason Zheng, Dec 16, 2005
    #9
  10. Davy

    John Penton Guest

    Davy wrote:
    > Hi,
    >
    > I work on Xilinx ISE, and my synthesis tool is XST and synplify.
    > I use verilog to write a Inverter Chain (delay ) like out =
    > ~(~(~(~...in)).
    > But the circuit be synthesised cancel all the invorter.
    >
    > How to synthesis out all the inverter chain I want?


    Again, noting other's comments about generating delays, the simplest way to
    do this is simply to instantiate them (and don't flatten).

    not_gate u_not_1 (
    .in (input),
    .out (sig1)
    );

    not_gate u_not_2 (
    .in (sig1),
    .out (output)
    );

    etc.

    --
    John Penton, posting as an individual unless specifically indicated
    otherwise.
    John Penton, Dec 19, 2005
    #10
  11. On 15 Dec 2005 19:35:22 -0800, "Davy" <> wrote:

    >Hi,
    >
    > I work on Xilinx ISE, and my synthesis tool is XST and synplify.
    > I use verilog to write a Inverter Chain (delay ) like out =
    >~(~(~(~...in)).
    > But the circuit be synthesised cancel all the invorter.
    >
    > How to synthesis out all the inverter chain I want?
    >
    >Any suggestions will be appreciated!
    >Best regards,
    >Davy


    There are some works about delay elements for asynchronous designs in
    Xilinx FPGA. Google for them.
    Javier Castillo, Dec 19, 2005
    #11
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