Is Component Instantiation possible inside 'if' ?

[deena102]

process(reset,clk)
variable temp1 : STD_LOGIC_VECTOR (output_width-1 DOWNTO 0);
begin
if(reset ='1')then
sum <= (others => '0');
prodmac <= (others => '0');
temp1 := (others => '0');
elsif( clk'event and clk ='0')then
if (nd ='1') then
m1: Mul16 port map(A,B,prodmac);
end if;

Is the Above instantiation of Component Mul16 Correct?? because i'm getting an error while compiling, 'Illegal Sequential Statement'

Help me please

 

[Ukanbal]

i do not understand why you tried to do a portmap inside a loop.
I have never seen a portmap inside a loop either... the only reason that comes to my mind is that you want Mul16 to be enabled when there is a rising edge of the clock. If this is what you want to implement just create an enable signal for your Mul16 and then set your enable to 1 inside the if loop.

 

[joris]

You can't do a component instantiation inside a process.
You'll have to use an enable 'bit' or something depending on the process, something like:

-- signal enableMul : std_logic defined

process(reset,clk)
variable temp1 : STD_LOGIC_VECTOR (output_width-1 DOWNTO 0);
begin
if(reset ='1')then
sum <= (others => '0');
prodmac <= (others => '0');
temp1 := (others => '0');
elsif( clk'event and clk ='0')then
if (nd ='1') then
enableMul <= '1';
else
enableMul <= '0';
end if;

m1: Mul16En port map(enableMul,A,B,prodmac);