Is "integer" a keyword of VHDL?

Discussion in 'VHDL' started by John, Sep 16, 2003.

  1. John

    John Guest

    Dear VHDL friends,

    I have a simple but basic question:

    Is "integer" a keyword of VHDL? then what is it?

    I cannot find "integer" in the keywords list of VHDL. I cannot find
    the definition in the ieee library either, e.g. ieee.std_logic.1164.
    But I do find the definition of "signed" or "unsigned" in the library.
    Then what is the "integer"? I do find "integer" in the VHDL '93
    Syntax. but it is meanless for me.

    please give me some hints.

    John
    John, Sep 16, 2003
    #1
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  2. On 16 Sep 2003 15:49:48 -0700, (John) wrote:

    >Dear VHDL friends,
    >
    >I have a simple but basic question:
    >
    >Is "integer" a keyword of VHDL? then what is it?
    >
    >I cannot find "integer" in the keywords list of VHDL. I cannot find
    >the definition in the ieee library either, e.g. ieee.std_logic.1164.
    >But I do find the definition of "signed" or "unsigned" in the library.
    >Then what is the "integer"? I do find "integer" in the VHDL '93
    >Syntax. but it is meanless for me.


    Yes, integer is a keyword. The definition of integer doesn't appear
    in any package source because integer is built in to the language; it
    doesn't need to be defined in a package.

    The VHDL integer type has similar semantics to the integer type in
    most other computer languages. It is defined to have *at least* the
    range -2**31 - 1 to +2**31 - 1. Most tools on 32 bit platforms will
    map this directly to a 32 bit twos comp number, which has a range of
    -2**31 to +2**31 - 1, and do not check for overflow.

    I suggest you avoid unconstrained integers when writing synthesisable
    code. Constrained integers (e.g. "integer range 0 to 31") will
    usually give more predictable results (a 5 bit value in this case),
    and will also have bounds checking during simulation (which means you
    find your bugs sooner).

    Note that there is no guarantee of the mapping between integer and the
    hardware. In theory, a synthesis tool could choose a mapping other
    than binary (such as one-hot or Gray). In practice, binary is always
    used. (Does anyone know of an exception?)
    You should avoid using integers (either constrained or unconstrained)
    for ports on reusable IP cores for this reason. Use signed, unsigned,
    or std_logic_vector instead.

    Note that signed and unsigned are *not* keywords; they are defined in
    packages, and may have different meanings depending on the packages
    used.

    You might like to read more about integers and integer <-> slv
    conversions in the FAQ:
    http://www.vhdl.org/comp.lang.vhdl/FAQ1.html

    Regards,
    Allan
    Allan Herriman, Sep 17, 2003
    #2
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  3. John

    John Guest

    Dear Allen,

    thank you very much for your post.

    > Yes, integer is a keyword. The definition of integer doesn't appear
    > in any package source because integer is built in to the language; it
    > doesn't need to be defined in a package.


    I cannot find integer as a keyword (or Reserved word) in the VHDL
    syntax, e.g. http://dz.ee.ethz.ch/support/ic/vhdl/vhdl93_syntax.html#keywords
    According to your words, there are some "hidden" keywords in the
    package source, now I would like to know: how many such hidden
    keywords are in the package source? Actually, you know I don't care
    the details inside the package source, but if I know what stuff inside
    source, I would be more comfortable.

    > I suggest you avoid unconstrained integers when writing synthesisable
    > code. Constrained integers (e.g. "integer range 0 to 31") will
    > usually give more predictable results (a 5 bit value in this case),
    > and will also have bounds checking during simulation (which means you
    > find your bugs sooner).


    Thank you very much for giving your this valuable suggestion.

    > You should avoid using integers (either constrained or unconstrained)
    > for ports on reusable IP cores for this reason. Use signed, unsigned,
    > or std_logic_vector instead.


    Thanks too.

    > You might like to read more about integers and integer <-> slv
    > conversions in the FAQ:
    > http://www.vhdl.org/comp.lang.vhdl/FAQ1.html


    I have read it again, now I feel I have understood it more.

    According to your answer, I feel you know inside VHDL very well. I
    would like to ask you another basic question, which is related to
    "="--equal operator.

    How VHDL define "=" at first step? based on integer data? Let me call
    this base"=".
    Because VHDL is a strongly typed language, package numeric_std defined
    overloaded"=" for different data types, and such definition should
    need base"=" in the definition of related function.
    Similar operators include ">", "<", "+", "-", etc.... all of them are
    based on integer at very beginning, do I understand correctly?

    Thanks again for your help.

    John
    John, Sep 17, 2003
    #3
  4. "John" <> schreef in bericht
    news:...
    > Dear Allen,
    >
    > thank you very much for your post.
    >
    > > Yes, integer is a keyword. The definition of integer doesn't appear
    > > in any package source because integer is built in to the language; it
    > > doesn't need to be defined in a package.

    >

    The types you are looking for are in chapter 3 of the VHDL standard.
    (Integer, real, bit, ....).

    > According to your answer, I feel you know inside VHDL very well. I
    > would like to ask you another basic question, which is related to
    > "="--equal operator.
    >
    > How VHDL define "=" at first step? based on integer data? Let me call
    > this base"=".
    > Because VHDL is a strongly typed language, package numeric_std defined
    > overloaded"=" for different data types, and such definition should
    > need base"=" in the definition of related function.
    > Similar operators include ">", "<", "+", "-", etc.... all of them are
    > based on integer at very beginning, do I understand correctly?


    If you declare a type, say:
    type mycolors is (red, yellow,green)
    then implictly the equality operators are declared. So you may write:
    variable t1, t2 : mycolors;
    if t1=t2 then ....
    This condition is only true of t1 is equal to t2.

    In case you don't like this implicit behaviour of the equality you may
    declare your own overloaded function in the same declaration area:
    function "="(a,b : mycolors) return boolean is
    ... and here the behaviour you like.

    Egbert Molenkamp
    Egbert Molenkamp, Sep 17, 2003
    #4
  5. John

    David Jones Guest

    In article <>,
    John <> wrote:
    >Dear VHDL friends,
    >
    >I have a simple but basic question:
    >
    >Is "integer" a keyword of VHDL? then what is it?
    >
    >I cannot find "integer" in the keywords list of VHDL. I cannot find
    >the definition in the ieee library either, e.g. ieee.std_logic.1164.
    >But I do find the definition of "signed" or "unsigned" in the library.
    >Then what is the "integer"? I do find "integer" in the VHDL '93
    >Syntax. but it is meanless for me.


    "integer" is a subtype of the "VHDL universal integer".

    It is predefined in STD.STANDARD, which is "built-in" to all VHDL
    compilers.

    As such, "integer" is not really a keyword. It is a subtype name
    entered into the compiler's symbol table prior to its analyzing any
    of your code.
    David Jones, Sep 18, 2003
    #5
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