Is it possible to define an alias of a type?

[TigerJade]

I tried the following codes:
Line 1: alias counter_type is std_logic_vector(11 downto 0);
Line 2: signal c : counter_type := (others => '0');

And what I got during synthesis (with Leonardo Spectrum) was an error:
Line 1: Syntax Error near '('.

Can anyone tell me what's wrong in my codes?

Thanks,

TJ

 

[Nicolas Matringe]

I tried the following codes:
Line 1: alias counter_type is std_logic_vector(11 downto 0);
Line 2: signal c : counter_type := (others => '0');
And what I got during synthesis (with Leonardo Spectrum) was an error:
Line 1: Syntax Error near '('.
Can anyone tell me what's wrong in my codes?

Hi
You can't use alias for types, use 'subtype' instead. Juste replace
'alias' by 'subtype' in your code.

Nicolas

 

[TigerJade]

Thanks, Nicolas.
I'm current working on a quite big project, which requires different
entities/blocks working together. However, to make the program easy to
read, I want to have these entities have their own types/subtypes,
which these types are actually the same thing and should be able to
interchangable between the interfaces of these blocks.
My original idea is to define type for all of these blocks and then use
alias in these blocks. Any suggestion on this problem?

TJ

 

[Mike Treseler]

I'm current working on a quite big project, which requires different
entities/blocks working together. However, to make the program easy to
read, I want to have these entities have their own types/subtypes,
which these types are actually the same thing and should be able to
interchangable between the interfaces of these blocks.
My original idea is to define type for all of these blocks and then use
alias in these blocks. Any suggestion on this problem?

I would recommend a little bit of bottom-up simulation work
before you lock yourself into a complex architecture.
Unless you have done this before, I would skip
the aliases as they are not observable in simulation.
If you are the only designer and this is a single
fpga, I would also minimize the number of entities.
Adding vector types will add ambiguity to assignments.
Stick to subtypes.

-- Mike Treseler

 

[Jonathan Bromley]

I'm current working on a quite big project, which requires different
entities/blocks working together. However, to make the program easy to
read, I want to have these entities have their own types/subtypes,
which these types are actually the same thing and should be able to
interchangable between the interfaces of these blocks.
My original idea is to define type for all of these blocks and then use
alias in these blocks. Any suggestion on this problem?

Put the subtype definitions in a package, and "use" the package
in each design unit that needs it. That's what packages are for.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.