Is it possible to impliment Blockram with a reset?

Discussion in 'VHDL' started by RaymondCaleatry, Jul 27, 2004.

  1. I am using the Xilinx webpack software, and have implimented a basic single
    port blockram, however, if i try to add any reset functionality, the
    Xilinx webpack synthesizer complains that it is no longer block ram. Is
    there any way to reset block ram to pre-deturmined settings.

    Raymond
    ----------------------------------------------
    process (PCI_CLK)
    begin
    if (PCI_CLK'event and PCI_CLK = '1') then
    if (we = '1') then
    CONFIG_SPACE(conv_integer(a)) <= di;
    end if;
    read_a <= a;
    end if;
    end process;

    spo <= CONFIG_SPACE(conv_integer(read_a));

    end syn;
    RaymondCaleatry, Jul 27, 2004
    #1
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  2. RaymondCaleatry wrote:
    > I am using the Xilinx webpack software, and have implimented a basic single
    > port blockram, however, if i try to add any reset functionality, the
    > Xilinx webpack synthesizer complains that it is no longer block ram. Is
    > there any way to reset block ram to pre-deturmined settings.


    No. It is possible to specify what values the RAM will contain when it
    comes out of configuration but it is not possible to reset the RAM once
    the device is in normal operation. This is done either with attributes
    in your VHDL or with "INIT" statements in your .UCF file. See the Xilinx
    documentation for details.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    Tim Hubberstey, Jul 27, 2004
    #2
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