No, VHDL doesn't offer disjoint ranges.
Pascal and Modula-xxx offer sets, which get you some of what
I suspect you want. Too bad they didn't make it into VHDL.
'e' (Verisity's verification language) has disjoint ranges for
subtypes. Vera may have such a thing too, but I don't know.
For some purposes it's cool to create a set lookalike in VHDL...
type t_charset is array(character) of boolean;
and then you can mess around creating sets from aggregates:
constant hex_digit: t_charset := (
'0' to '9' => TRUE,
'A' to 'F' => TRUE,
others => FALSE );
With a bit more work you could overload "and", "or" and
other operators to mimic the usual set operations.
--
Jonathan Bromley, Consultant
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