I have the same exact piece of code written twice. The only difference is that a "+" in one becomes a "-" in the other. In the one where there's the "+", the simulated latency (with respect to a change in the input "runvector") is 2 dataclk's, and the one where there's the "-", the simulated latency is 3 dataclks.
Is this somehow right? Here's my code:
Is this somehow right? Here's my code:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_SIGNED.all;
entity mult_runvector_add_offset is
port ( dataclk : in std_logic;
oneQN_A : in std_logic_vector(34 downto 0);
oneQN_B : in std_logic_vector(34 downto 0);
runvector : in std_logic_vector(8 downto 0);
mem_ready_A : out std_logic_vector(9 downto 0);
mem_ready_B : out std_logic_vector(9 downto 0));
end mult_runvector_add_offset;
architecture behavior of mult_runvector_add_offset is
signal mult_runvector_A : std_logic_vector(45 downto 0) := (others=>'0');
signal mult_runvector_B : std_logic_vector(45 downto 0) := (others=>'0');
signal added_offset_A : std_logic_vector(11 downto 0) := (others=>'0');
signal added_offset_B : std_logic_vector(11 downto 0) := (others=>'0');
begin
process(dataclk)
begin
if(dataclk'event and dataclk='1')then
mult_runvector_A <= oneQN_A * ('0' & runvector & '1');
mult_runvector_B <= oneQN_B * ('0' & runvector & '1');
added_offset_A <= "001100000000" + mult_runvector_A(44 downto 33);
added_offset_B <= "001100000000" - mult_runvector_B(44 downto 33);
end if;
end process;
mem_ready_A <= added_offset_A(10 downto 1);
mem_ready_B <= added_offset_B(10 downto 1);
end behavior;