Is there a way to combine verilog and vhdl?

Discussion in 'VHDL' started by alomar, Nov 15, 2006.

  1. alomar

    alomar

    Joined:
    Nov 15, 2006
    Messages:
    1
    I have a component written in vhdl and I want to use it in some instance written in verilog.

    Is there a way to combine them together or I must rewrite the vhdl component? If any, please tell me how to do this.

    Thanks for your help.
    alomar, Nov 15, 2006
    #1
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  2. alomar

    VHDL-BEGINNER

    Joined:
    Nov 14, 2006
    Messages:
    4
    yes you can do that.

    you should create a symbol file of both components. With using the block editor you can choose these symbol files and can place them there. Now you can connect al the I/O´s of them as you want. The block editor file must be your top-design.

    Good luck

    (Sorry for my bad english)
    Last edited: Nov 17, 2006
    VHDL-BEGINNER, Nov 15, 2006
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