is this a toggle ?!

Discussion in 'VHDL' started by Amit, Oct 9, 2007.

  1. Amit

    Amit Guest

    Hi group,

    I'm working on project (basic) to learn VHDL and the purpose of
    process (which had made so confused and mad). Anyway, I have question
    and need to know how I can create a toggle flipflop using D f/f.

    This is what that I think it should be but don't know how to get a
    confirm so I will appreciate it if somebody could tell me if I'm on a
    right track or no (the same as process);

    What it must be is the output (q) which clocks another component and
    qbar which goes back in d (input). Any comment?



    LIBRARY ieee;
    USE ieee.std_logic_1164.all;


    ENTITY toggle IS

    PORT(

    d: IN STD_LOGIC;
    rcClk: IN STD_LOGIC;
    q: BUFFER STD_LOGIC;

    qbar: OUT STD_LOGIC
    );

    END toggle ;


    ARCHITECTURE beh OF toggle IS
    BEGIN

    PROCESS(rcClk)
    BEGIN

    IF (rcClk'EVENT AND rcClk = '1') THEN

    q <= d;

    END IF;

    END PROCESS;

    qbar <= NOT (q);

    END beh;
    Amit, Oct 9, 2007
    #1
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  2. Amit

    Amit Guest

    On Oct 9, 10:26 am, Amit <> wrote:
    > Hi group,
    >
    > I'm working on project (basic) to learn VHDL and the purpose of
    > process (which had made so confused and mad). Anyway, I have question
    > and need to know how I can create a toggle flipflop using D f/f.
    >
    > This is what that I think it should be but don't know how to get a
    > confirm so I will appreciate it if somebody could tell me if I'm on a
    > right track or no (the same as process);
    >
    > What it must be is the output (q) which clocks another component and
    > qbar which goes back in d (input). Any comment?
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.all;
    >
    > ENTITY toggle IS
    >
    > PORT(
    >
    > d: IN STD_LOGIC;
    > rcClk: IN STD_LOGIC;
    > q: BUFFER STD_LOGIC;
    >
    > qbar: OUT STD_LOGIC
    > );
    >
    > END toggle ;
    >
    > ARCHITECTURE beh OF toggle IS
    > BEGIN
    >
    > PROCESS(rcClk)
    > BEGIN
    >
    > IF (rcClk'EVENT AND rcClk = '1') THEN
    >
    > q <= d;
    >
    > END IF;
    >
    > END PROCESS;
    >
    > qbar <= NOT (q);
    >
    > END beh;




    Ok, now I think this must the one. Would you please consider the
    following code instead?
    I have changed inteface modes



    ENTITY toggle IS

    PORT(

    d: IN STD_LOGIC;
    rcClk: IN STD_LOGIC;
    q: BUFFER STD_LOGIC;


    --qbar: OUT STD_LOGIC
    qbar: BUFFER STD_LOGIC
    );

    END toggle;


    ARCHITECTURE beh OF toggle IS
    BEGIN

    PROCESS(rcClk)
    BEGIN

    IF (rcClk'EVENT AND rcClk = '1') THEN

    --q <= d;
    q <= qbar;

    END IF;

    END PROCESS;

    qbar <= NOT (q);

    END beh;
    Amit, Oct 9, 2007
    #2
    1. Advertising

  3. Amit

    KJ Guest

    <Snip>

    You may want to consider putting a bit more thought into the question
    that you'd like the group to answer before just posting code and
    simply asking 'Any comments?'.

    My comments
    1. Your design works exactly as written.
    2. Your design may not work as you intended (but without any
    description from you it's not clear what your intended design should
    be).
    3. I'll bet signal 'q' has trouble getting out of the 'U' state.

    KJ
    KJ, Oct 9, 2007
    #3
  4. Amit

    Amit Guest

    On Oct 9, 11:26 am, KJ <> wrote:
    > <Snip>
    >
    > You may want to consider putting a bit more thought into the question
    > that you'd like the group to answer before just posting code and
    > simply asking 'Any comments?'.
    >
    > My comments
    > 1. Your design works exactly as written.
    > 2. Your design may not work as you intended (but without any
    > description from you it's not clear what your intended design should
    > be).
    > 3. I'll bet signal 'q' has trouble getting out of the 'U' state.
    >
    > KJ



    Thanks I had no idea.
    Amit, Oct 9, 2007
    #4
  5. Amit wrote:

    >> I'm working on project (basic) to learn VHDL and the purpose of
    >> process (which had made so confused and mad).


    This is a good example of wires
    getting in the way of a logical
    description. I expect that the
    operation you need could be
    described as

    if t = '1' then
    toggle_v := not toggle_v;
    end if;

    The missing piece is a synchronous
    template in which to insert this procedure.

    I would do it as shown below.

    -- Mike Treseler

    __________________________________

    library ieee;
    use ieee.std_logic_1164.all;

    entity toggle is
    port (
    clock : in std_ulogic;
    reset : in std_ulogic;
    t : in std_ulogic;
    q : out std_ulogic
    );

    end entity toggle;

    architecture synth of toggle is
    begin
    toggle : process(reset, clock) is
    variable toggle_v : std_ulogic ;
    ------------------------------------------------------------------
    -- Template Procedures: Always same three names. Contents varies.
    ------------------------------------------------------------------
    procedure init_regs is -- init of register variables only
    begin
    toggle_v := '0';
    end procedure init_regs;
    ------------------------------------------------------------------
    procedure update_regs is -- distilled functional description
    begin
    if t = '1' then
    toggle_v := not toggle_v;
    end if;
    end procedure update_regs;
    ------------------------------------------------------------------
    procedure update_ports is -- wire register variables out to port
    begin
    q <= toggle_v;
    end procedure update_ports;

    ------------------------------------------------------------------
    -- Single Process Template -- Always exactly the same:
    ------------------------------------------------------------------
    begin -- process template
    if reset = '1' then
    init_regs;
    elsif rising_edge(clock) then
    update_regs;
    end if;
    update_ports;
    end process toggle;
    end architecture synth;
    Mike Treseler, Oct 9, 2007
    #5
  6. Amit

    Amit Guest

    On Oct 9, 12:53 pm, Mike Treseler <> wrote:
    > Amit wrote:
    > >> I'm working on project (basic) to learn VHDL and the purpose of
    > >> process (which had made so confused and mad).

    >
    > This is a good example of wires
    > getting in the way of a logical
    > description. I expect that the
    > operation you need could be
    > described as
    >
    > if t = '1' then
    > toggle_v := not toggle_v;
    > end if;
    >
    > The missing piece is a synchronous
    > template in which to insert this procedure.
    >
    > I would do it as shown below.
    >
    > -- Mike Treseler
    >
    > __________________________________
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > entity toggle is
    > port (
    > clock : in std_ulogic;
    > reset : in std_ulogic;
    > t : in std_ulogic;
    > q : out std_ulogic
    > );
    >
    > end entity toggle;
    >
    > architecture synth of toggle is
    > begin
    > toggle : process(reset, clock) is
    > variable toggle_v : std_ulogic ;
    > ------------------------------------------------------------------
    > -- Template Procedures: Always same three names. Contents varies.
    > ------------------------------------------------------------------
    > procedure init_regs is -- init of register variables only
    > begin
    > toggle_v := '0';
    > end procedure init_regs;
    > ------------------------------------------------------------------
    > procedure update_regs is -- distilled functional description
    > begin
    > if t = '1' then
    > toggle_v := not toggle_v;
    > end if;
    > end procedure update_regs;
    > ------------------------------------------------------------------
    > procedure update_ports is -- wire register variables out to port
    > begin
    > q <= toggle_v;
    > end procedure update_ports;
    >
    > ------------------------------------------------------------------
    > -- Single Process Template -- Always exactly the same:
    > ------------------------------------------------------------------
    > begin -- process template
    > if reset = '1' then
    > init_regs;
    > elsif rising_edge(clock) then
    > update_regs;
    > end if;
    > update_ports;
    > end process toggle;
    > end architecture synth;



    Mike THANK YOU so much. I have not read about procedure yet but this
    will be a good start. However, it is possible to make it work without
    PROCEDURE? what I was thinking about a toggling f/f was that only with
    these input and outputs:

    d (input) q(output)

    clk qBar (output)

    where q goes out and qbar gets into the d.

    any advice?

    Regards,
    ak
    Amit, Oct 9, 2007
    #6
  7. Amit wrote:

    > any advice?


    Hire a tutor or a consultant.

    -- Mike Treseler
    Mike Treseler, Oct 9, 2007
    #7
  8. Amit

    KJ Guest

    "Amit" <> wrote in message
    news:...
    > On Oct 9, 11:26 am, KJ <> wrote:
    >> <Snip>


    >>
    >> You may want to consider putting a bit more thought into the question
    >> that you'd like the group to answer before just posting code and
    >> simply asking 'Any comments?'.
    >>
    >> My comments
    >> 1. Your design works exactly as written.
    >> 2. Your design may not work as you intended (but without any
    >> description from you it's not clear what your intended design should
    >> be).
    >> 3. I'll bet signal 'q' has trouble getting out of the 'U' state.
    >>
    >> KJ

    >


    >
    > Thanks I had no idea.
    >

    That much is clear

    Going back to the opening paragraphs of your original post....
    > I'm working on project (basic) to learn VHDL and the purpose of
    > process (which had made so confused and mad).

    Since you're trying to learn VHDL, it won't help much if anyone here gives
    you the answer but I suppose a little guidance can't hurt.

    > Anyway, I have question
    > and need to know how I can create a toggle flipflop using D f/f.
    >

    Fair enough...but first you have to have the entity/architecture code for a
    D flip flop. I'm not saying it's difficult to create but you do need to
    have it to do your assignment and the first thing you'll need to do is
    decide on the interface to that entity. Your basic run of the mill D flip
    flop has only 'Clock' and 'D' as inputs and 'Q' as an output, that's it.
    Fancier ones may have a 'Qbar' output and a 'Reset' input but they don't
    have to. Anyway, decide on the interface you want for your D flip flop and
    then code up the entity and then the architecture. Debug it to make sure it
    is correct.

    Now that the D flip flop is done, you have to USE it to create a toggle flip
    flop. Using something does not mean changing it, it means to create an
    instance of it and connect it up appropriately for you usage. What this
    means is that when you finally get to the architecture code for the toggle
    flip flop you will
    - Instantiate the previously created D flip flop. (Ex: My_Dff : entity
    work.D_FF port map(.....);
    - Do not change ANY of the code for the D flip flop itself...you've debugged
    it, it's working, leave it alone.

    But first you again need to decide on what the interface is to your toggle
    flip flop. Your basic run of the mill toggle flip flop has 'T', 'Clock' and
    'Reset' inputs and a 'Q' output (again fancier ones may have 'Qbar' if you
    feel it is appropriate). You'll notice that I list 'Reset' as one of the
    'must have' inputs but I'll leave it to you to work out why a toggle flip
    flop should always have a reset but a D flip flop does not.

    Just like before with the D flip flop, work out what you want the interface
    to be to your toggle flip flop and now you'll have the entity code for your
    toggle flip flop. To do the architecture of the toggle flip flop, first
    instanitate the D flip flop using the example above (since that is part of
    the assignment). Now work out the logic you need to connect the input and
    outputs appropriately.

    The assignment is (I'm guessing) supposed to get you to think about
    hierarchical design, breaking down a 'big' problem into a number of 'small'
    problems, tying them together appropriately with wires and additional logic
    if necessary. In this case, you've been told the hierarchy (toggle flip
    flop made out of a D flip flop), you may also have been told the interfaces
    (i.e. the VHDL entity) and it's up to you to work out the details in the
    architecture body.

    > This is what that I think it should be but don't know how to get a
    > confirm so I will appreciate it if somebody could tell me if I'm on a
    > right track or no (the same as process);

    You don't need people in a newsgroup to confirm that you're on the right
    track. You simply need to read the assignment definition and then test your
    design with a simulator.

    Good luck on your studies

    KJ
    KJ, Oct 10, 2007
    #8
  9. Amit

    Dave Pollum Guest

    On Oct 9, 4:23 pm, Amit <> wrote:
    > On Oct 9, 12:53 pm, Mike Treseler <> wrote:
    >
    >
    >
    > > Amit wrote:
    > > >> I'm working on project (basic) to learn VHDL and the purpose of
    > > >> process (which had made so confused and mad).

    >
    > > This is a good example of wires
    > > getting in the way of a logical
    > > description. I expect that the
    > > operation you need could be
    > > described as

    >
    > > if t = '1' then
    > > toggle_v := not toggle_v;
    > > end if;

    >
    > > The missing piece is a synchronous
    > > template in which to insert this procedure.

    >
    > > I would do it as shown below.

    >
    > > -- Mike Treseler

    >
    > > __________________________________

    >
    > > library ieee;
    > > use ieee.std_logic_1164.all;

    >
    > > entity toggle is
    > > port (
    > > clock : in std_ulogic;
    > > reset : in std_ulogic;
    > > t : in std_ulogic;
    > > q : out std_ulogic
    > > );

    >
    > > end entity toggle;

    >
    > > architecture synth of toggle is
    > > begin
    > > toggle : process(reset, clock) is
    > > variable toggle_v : std_ulogic ;
    > > ------------------------------------------------------------------
    > > -- Template Procedures: Always same three names. Contents varies.
    > > ------------------------------------------------------------------
    > > procedure init_regs is -- init of register variables only
    > > begin
    > > toggle_v := '0';
    > > end procedure init_regs;
    > > ------------------------------------------------------------------
    > > procedure update_regs is -- distilled functional description
    > > begin
    > > if t = '1' then
    > > toggle_v := not toggle_v;
    > > end if;
    > > end procedure update_regs;
    > > ------------------------------------------------------------------
    > > procedure update_ports is -- wire register variables out to port
    > > begin
    > > q <= toggle_v;
    > > end procedure update_ports;

    >
    > > ------------------------------------------------------------------
    > > -- Single Process Template -- Always exactly the same:
    > > ------------------------------------------------------------------
    > > begin -- process template
    > > if reset = '1' then
    > > init_regs;
    > > elsif rising_edge(clock) then
    > > update_regs;
    > > end if;
    > > update_ports;
    > > end process toggle;
    > > end architecture synth;

    >
    > Mike THANK YOU so much. I have not read about procedure yet but this
    > will be a good start. However, it is possible to make it work without
    > PROCEDURE? what I was thinking about a toggling f/f was that only with
    > these input and outputs:
    >
    > d (input) q(output)
    >
    > clk qBar (output)
    >
    > where q goes out and qbar gets into the d.
    >
    > any advice?
    >
    > Regards,
    > ak


    Amit;
    I highly recommend the book "Essential VHDL: RTL Synthesis Done Right"
    as a good beginner's book. From the book's back cover: "Essential
    VHDL starts with simple examples and slowly builds to cover the most
    comples topics. It's great for the VHDL novice..."
    HTH
    -Dave Pollum
    Dave Pollum, Oct 10, 2007
    #9
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