Is this kind of writing useful?

Discussion in 'VHDL' started by fl, Mar 2, 2013.

  1. fl

    fl Guest

    Hi,
    I get the following VHDL code from Matlab HDL coder, in which enb_1_1_1 always is '1' from its input. I find the process to write dbfout1_re_tmp value while out of the process the reverse is written to dbfout1_re.

    What do you think of this writing style? Is it an acceptable even for a hand writing code? Is there any other better writing style?


    Thanks,





    .......................
    temp_process26_Delay_butterfly1 : PROCESS (clk, reset)
    BEGIN
    IF reset = '1' THEN
    dbfout1_re_tmp <= (OTHERS => '0');
    dbfout1_im_tmp <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
    IF enb_1_1_1 = '1' THEN
    dbfout1_re_tmp <= bfout1_re;
    dbfout1_im_tmp <= bfout1_im;
    END IF;
    END IF;
    END PROCESS temp_process26_Delay_butterfly1;

    dbfout1_re <= std_logic_vector(dbfout1_re_tmp);
    dbfout1_im <= std_logic_vector(dbfout1_im_tmp);
    fl, Mar 2, 2013
    #1
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  2. fl

    Tricky Guest

    On Saturday, March 2, 2013 3:17:45 AM UTC, fl wrote:
    > Hi,
    >
    > I get the following VHDL code from Matlab HDL coder, in which enb_1_1_1 always is '1' from its input. I find the process to write dbfout1_re_tmp value while out of the process the reverse is written to dbfout1_re.
    >
    >
    >
    > What do you think of this writing style? Is it an acceptable even for a hand writing code? Is there any other better writing style?
    >
    >
    >
    >
    >
    > Thanks,
    >
    >
    >
    >
    >
    >
    >
    >
    >
    >
    >
    > ......................
    >
    > temp_process26_Delay_butterfly1 : PROCESS (clk, reset)
    >
    > BEGIN
    >
    > IF reset = '1' THEN
    >
    > dbfout1_re_tmp <= (OTHERS => '0');
    >
    > dbfout1_im_tmp <= (OTHERS => '0');
    >
    > ELSIF clk'event AND clk = '1' THEN
    >
    > IF enb_1_1_1 = '1' THEN
    >
    > dbfout1_re_tmp <= bfout1_re;
    >
    > dbfout1_im_tmp <= bfout1_im;
    >
    > END IF;
    >
    > END IF;
    >
    > END PROCESS temp_process26_Delay_butterfly1;
    >
    >
    >
    > dbfout1_re <= std_logic_vector(dbfout1_re_tmp);
    >
    > dbfout1_im <= std_logic_vector(dbfout1_im_tmp);


    HDL Coder produces usable but crap to read code.
    It works ok, but I wouldnt wasnt to read it. God forbid you have to modify it by hand.

    But then you're not supposed to modify it by hand. You're supposed to modify the top level file. THe problem with this is, if you add more blocks or rename anything, you have to manually remove the old filenames and add in the 100s of new files HDL crapper generates (unless you can script it up - but HDL coder used to have a nice bug where it wouldnt generate any other TCLthan the deafult - no matter what you put in the "script output box".

    Can you tell I try and avoid HDL coder whenever possible?
    Tricky, Mar 4, 2013
    #2
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  3. fl

    Andy Guest

    On Friday, March 1, 2013 9:17:45 PM UTC-6, fl wrote:
    > Hi, I get the following VHDL code from Matlab HDL coder, in which enb_1_1_1 always is '1' from its input. I find the process to write dbfout1_re_tmpvalue while out of the process the reverse is written to dbfout1_re. What do you think of this writing style? Is it an acceptable even for a hand writing code? Is there any other better writing style? Thanks, ....................... temp_process26_Delay_butterfly1 : PROCESS (clk, reset) BEGIN IF reset = '1' THEN dbfout1_re_tmp <= (OTHERS => '0'); dbfout1_im_tmp <= (OTHERS => '0'); ELSIF clk'event AND clk = '1' THEN IF enb_1_1_1 = '1' THEN dbfout1_re_tmp <= bfout1_re; dbfout1_im_tmp <= bfout1_im; END IF; END IF; END PROCESS temp_process26_Delay_butterfly1; dbfout1_re <= std_logic_vector(dbfout1_re_tmp); dbfout1_im <= std_logic_vector(dbfout1_im_tmp);


    This style may have to do with the generator not being aware of whether the_tmp signal is read back in the process, while the final signal may be a port of mode out (and therefore not readable under pre-2008 VHDL).

    I would not recommend this style in hand written code unless the value driving the output port needs to also be read (e.g. for feedback).

    I also noticed the type convertion in the final assignments. This may also be part of the reason the generator created this style of code.

    In general, there are very few style elements of machine-generated vhdl that I would consider desirable for human-written code.

    Andy
    Andy, Mar 4, 2013
    #3
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