# Is this Multi-Cycle Path ?

Discussion in 'VHDL' started by Ved, Jan 10, 2007.

1. ### VedGuest

Hi all,
I have a design which has 15 blocks.
Data enters from 1st block and after 60 clocks comes out from 15th
block.
I control enabling of each block by using a counter which counts till
60 at each clock (same clock as above).
So this counter output(say count) goes to every block and every block
has statements something like this :

Blcok 1:
If count >=2 than
-----Do something
end if;

Blcok 2:
If count >=4 than
-----Do something
end if;

Blcok 3:
If count >=7 than
-----Do something
end if;

Blcok 4:
If count >=18 than
-----Do something
end if;

................and so on.

Blcok 15:
If count >=18 than
-----Do something
end if;

My question is that is the data going in block 1 and being processed
through all the blocks and than coming out of block 15 will be a
Multi-Cycle path ?
And why ?

regards ved

Ved, Jan 10, 2007

2. ### Jim LewisGuest

Ved,
Can't answer your question directly without more information.
I will answer your question indirectly:

A pipeline separates multiple states of combinational
logic with registers. Below c1 through c4 are blocks
of combinational logic. "|" is a register:

in -- | c1 | c2 | c3 | c4 | -- out

Lets suppose that each block plus register will
perform at 10 ns clock boundaries. I constrain the
design for 10 ns clock, synthesize, and life is good.

Multicycle path says that in some technologies
registers are expensive (such as an ASIC but not
most FPGAs), so lets remove the internal registers:

in -- | c1 c2 c3 c4 | -- out

Since the pipelined design ran at 10 ns, this
one should be able to run at 40 ns. However, we
want to run the design at 10 ns. If we only need
an output once every 40 ns, then we can add control
signals (to capture in and out at the appropriate time)
and tell the synthesis tool that this is a multicycle
path. Make sure to capture the output only when it is
stable - especially if the object in the datapath
is used as status or control to some other piece of
logic.

Pipelining summary:
1) provides a result once every clock once
the pipeline gets filled.
2) no extra timing constraints - so no risk.
3) Costs an extra register if the technology (ASIC)
does not absorb it into a cell with combinational
logic. Note that in most FPGAs, the cost is nothing.

Multicycle Summary:
1) Produces a result, once every several clocks
2) Need to add timing constraints to identify the path
3) Be very careful to capture input and output values
at appropriate times.

In general, I will do pipelining unless there is some area
concern in an ASIC (which there usually is not) or some reason
it is not easy to do pipelining (such as a data in bus to a chip
that goes everywhere and as a result is slow).

With your problem, if there are registers between the stages
you describe then it is pipelining, if not then it is a
multicycle path.

Cheers,
Jim

> Hi all,
> I have a design which has 15 blocks.
> Data enters from 1st block and after 60 clocks comes out from 15th
> block.
> I control enabling of each block by using a counter which counts till
> 60 at each clock (same clock as above).
> So this counter output(say count) goes to every block and every block
> has statements something like this :
>
> Blcok 1:
> If count >=2 than
> -----Do something
> end if;
>
> Blcok 2:
> If count >=4 than
> -----Do something
> end if;
>
> Blcok 3:
> If count >=7 than
> -----Do something
> end if;
>
> Blcok 4:
> If count >=18 than
> -----Do something
> end if;
>
> ...............and so on.
>
> Blcok 15:
> If count >=18 than
> -----Do something
> end if;
>
>
> My question is that is the data going in block 1 and being processed
> through all the blocks and than coming out of block 15 will be a
> Multi-Cycle path ?
> And why ?
>
>
> regards ved
>

Jim Lewis, Jan 10, 2007

## Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.