ISE6.1: Constant definition in package doesn't work

Discussion in 'VHDL' started by Erik Markert, Sep 25, 2003.

  1. Erik Markert

    Erik Markert Guest

    Hello,

    I have a package with a function and some constant definitions. Now I
    implement it to the project. In Modelsim I can access the constants but
    in ISE6.1 Synthesis it doesn't find that constant.

    Code:
    package body fpga_config_pack IS
    CONSTANT deviceID : bit_vector(15 downto 0):= X"0815" ;
    function calc_par (SIGNAL ad: std_logic_vector ) return std_logic IS
    ....
    END;
    END fpga_config_pack;

    use work.fpga_config_pack.ALL;
    ENTITY ...

    ARCHITECTURE rtl_A...
    BEGIN
    data(0) <= calc_par(address);
    data <= TO_STDLOGICVECTOR(deviceID);
    END rtl_A;

    The Synthesize XST has no problems with calc_par() but reports an error
    with the constant:
    Compiling vhdl file C:/Xilinx/PCI_Card/fpga_config_pack.vhd in Library work.
    Architecture fpga_config_pack of Entity fpga_config_pack is up to date.
    Compiling vhdl file C:/Xilinx/PCI_Card/config_space.vhd in Library work.
    ERROR:HDLParsers:3312 - C:/Xilinx/PCI_Card/config_space.vhd Line 62.
    Undefined symbol 'deviceID'.

    In Modelsim standalone simulation all works fine.
    What's the mistake in ISE6.1?

    Thanks

    Erik
    --
    \\Erik Markert - student of Information Technology//
    \\ at Chemnitz University of Technology //
    \\ TalkTo: -chemnitz.de //
    \\ URL: http://www.erikmarkert.de //
    Erik Markert, Sep 25, 2003
    #1
    1. Advertising

  2. Erik Markert wrote:

    > package body fpga_config_pack IS
    > CONSTANT deviceID : bit_vector(15 downto 0):= X"0815" ;


    > ERROR:HDLParsers:3312 - C:/Xilinx/PCI_Card/config_space.vhd Line 62.
    > Undefined symbol 'deviceID'.
    >
    > In Modelsim standalone simulation all works fine.
    > What's the mistake in ISE6.1?


    Your problem is consistent with ISE6.1 set to '87 instead of '93.

    -- Mike Treseler
    Mike Treseler, Sep 25, 2003
    #2
    1. Advertising

  3. Erik Markert

    Erik Markert Guest

    Mike Treseler wrote:

    >
    > Your problem is consistent with ISE6.1 set to '87 instead of '93.


    But constant declaration in packages should be also possible in '87? Or
    is there something different in including that library?

    Erik
    --
    \\Erik Markert - student of Information Technology//
    \\ at Chemnitz University of Technology //
    \\ TalkTo: -chemnitz.de //
    \\ URL: http://www.erikmarkert.de //
    Erik Markert, Sep 25, 2003
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. buke2
    Replies:
    0
    Views:
    561
    buke2
    Aug 12, 2004
  2. Benjamin Todd

    Access Type Unsupported ISE6.2.03i

    Benjamin Todd, Oct 19, 2004, in forum: VHDL
    Replies:
    5
    Views:
    724
    Charles M. Elias
    Oct 19, 2004
  3. Tim Verstraete
    Replies:
    1
    Views:
    557
    Mike Treseler
    Sep 12, 2005
  4. Jianli Shen
    Replies:
    1
    Views:
    569
    Victor Bazarov
    Mar 13, 2005
  5. Ark
    Replies:
    1
    Views:
    406
    Chris Torek
    Aug 7, 2004
Loading...

Share This Page