issue when using to_SFix

Discussion in 'VHDL' started by axr0284, Jan 19, 2010.

  1. axr0284

    axr0284 Guest

    Hi,
    I tried using to_SFix from the IEEE fixed point package but I am
    getting this error. I am using Active HDL as the simulator.
    <CODE>
    entity scaler is
    generic(
    GAIN_FRACTIONAL_BITS : integer := 4;
    GAIN_INTEGER_BITS : integer := 12

    );
    port(
    gain : in std_logic_vector((GAIN_FRACTIONAL_BITS +
    GAIN_INTEGER_BITS)-1 downto 0)
    );
    end scaler;

    architecture scaler of scaler is

    signal s_gain : sfixed(GAIN_INTEGER_BITS-1 downto -
    GAIN_FRACTIONAL_BITS);

    begin

    s_gain <= to_SFix(gain, GAIN_INTEGER_BITS, GAIN_FRACTIONAL_BITS);

    end scaler;
    </CODE>

    The error I am getting is the following:
    # EXECUTION:: ERROR : :work:fixed_generic_pkg:TO_SFIX
    (STD_ULOGIC_VECTOR) Vector lengths do not match. Input length is 16
    and output will be 12 wide.

    # RUNTIME: Fatal Error: RUNTIME_0046 scaler.vhd (71): Incompatible
    ranges; left: (11 downto -4), right: (null range).

    Anybody can help me figure this out. Thanks a lot.
    Amish
    axr0284, Jan 19, 2010
    #1
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