Issues using files in VHDL

Discussion in 'VHDL' started by Subramanian Ramaswamy, Jun 26, 2003.

  1. I am trying to initialize a 16 bit shift register from a file which contains
    "0000000000000000" using the following code. However, when simulating the
    value in the file is not absorbed into the output or to the variable "val"
    that I have used. If some one can help me figure out what the problem is, I
    would appreciate it.

    Thanks.

    library IEEE;


    use IEEE.STD_LOGIC_1164.all;
    use std.textio.all;
    entity ShiftReg is
    Port (d_in : in std_logic_vector(15 downto 0);
    serial_in,ld,shift,clk,reset : in std_logic;
    q : inout std_logic_vector(15 downto 0));
    end entity ShiftReg;

    architecture behavioral of ShiftReg is
    subtype word is std_logic_vector(15 downto 0);
    type initz is file of word;
    begin
    P: process (clk, shift, ld,reset)
    file datain : initz open read_mode is "init.txt";

    begin
    if (reset='1') then
    while not(endfile(datain)) loop
    read(datain,val);
    end loop;
    q <=val;
    elsif ( clk'event and clk ='1') then
    if (shift = '0') and (ld='1') then
    q <= d_in ;
    elsif (shift = '1') then
    q(14 downto 0) <= q(15 downto 1) ;
    q(15) <= serial_in ;
    end if;
    end if;
    end process P;
    end architecture behavioral;
     
    Subramanian Ramaswamy, Jun 26, 2003
    #1
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  2. Subramanian Ramaswamy

    VhdlCohen Guest

    >architecture behavioral of ShiftReg is
    > subtype word is std_logic_vector(15 downto 0);
    > type initz is file of word;
    >begin
    > P: process (clk, shift, ld,reset)
    > file datain : initz open read_mode is "init.txt";
    >
    > begin
    > if (reset='1') then
    > while not(endfile(datain)) loop
    > read(datain,val);
    > end loop;


    You need a line declaration, and a readline before the read.
    Thus:
    begin
    P: process (clk, shift, ld,reset)
    file datain : initz open read_mode is "init.txt";
    variable L : Line; -- NEW

    begin
    if (reset='1') then
    while not(endfile(datain)) loop
    readline(datain, L); -- NEW, read a line into L
    read(L,val); -- Changed, read from Line into your variable
    end loop;

    ----
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
     
    VhdlCohen, Jun 26, 2003
    #2
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  3. Hi,

    "VhdlCohen" <> wrote in message
    news:...
    <SNIP>>
    > You need a line declaration, and a readline before the read.
    > Thus:
    > begin
    > P: process (clk, shift, ld,reset)
    > file datain : initz open read_mode is "init.txt";
    > variable L : Line; -- NEW
    >


    Not sure if that's enough, as the file being opened is NOT of TEXT type, a
    new type named "initz", in which case the predefined/overloaded by TEXTIO
    procedures *may* not work. Infact I tried it and Modelsim 5.4 doesn't
    compile (neither does NC), as a general suggestion the OP (Original Poster)
    may want to stick to TEXT file type. (I am sure that Ben already knows this
    problem and much much more).

    > begin
    > if (reset='1') then
    > while not(endfile(datain)) loop
    > readline(datain, L); -- NEW, read a line into L
    > read(L,val); -- Changed, read from Line into your variable



    Another good idea would be to use the GOOD flag returned by the READ
    procedure, it can help in catching any erros in the READ procedure.

    Regards,
    Srinivasan

    > end loop;
    >


    --
    Srinivasan Venkataramanan
    Senior Verification Engineer
    Software & Silicon Systems India Pvt Ltd. - an Intel company
    Bangalore, India

    http://www.noveldv.com http://www.deeps.org

    I don't speak for Intel
     
    Srinivasan Venkataramanan, Jun 27, 2003
    #3
  4. Subramanian Ramaswamy

    jaisree

    Joined:
    Mar 17, 2009
    Messages:
    1
    fileread doubt

    Hi,
    I can run the code and see the output... bt the systhesis report SHOWING error for this code below. plz help me to view systhesis report..

    process(rst)
    file load: text open read_mode is "F:\VHDLfiles\input.txt";
    variable ab : line;
    variable sto : integer;
    begin
    if rst = '1' then
    for address in 1 to 16384 loop
    readline(load,ab);
    read(ab,sto);
    if address mod 2 /= 0 then
    ramodd(address1) := sto;
    address1 := address1 + 1;
    elsif address mod 2 = 0 then
    rameven(address2) := sto;
    address2 := address2 + 1;
    end if;
    end loop;
    end if;
    end process;

    report showing error:Xst:1914 - file <load> does not exist.
     
    Last edited: Mar 19, 2009
    jaisree, Mar 17, 2009
    #4
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