jtag/ATPG and read-only registers

Discussion in 'VHDL' started by Calvin, Nov 23, 2005.

  1. Calvin

    Calvin Guest

    Is there any way I can write vhdl codes for testability for read-only
    registers in FPGA or ASIC ?

    Muxing using the test mode pin is not acceptable since its value may be
    flipped by exposing to radiation and leading to erroreneous writes.

    I heard that we can use jtag or ATPG to check out read-only registers
    during testing. Please share with us your experience or expertise.

    Many thanks in advance.

    Calvin
     
    Calvin, Nov 23, 2005
    #1
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