Latches problem

Discussion in 'VHDL' started by aaaaaa, May 5, 2005.

  1. aaaaaa

    aaaaaa Guest

    Hi guyes,
    Just see the process !
    RDI output signals are not being latched . At reset '0' , all signals
    become low but as soon as reset becomes high , all RDI outputs become
    high. and after that they are being latched properly.
    Pl suggest what should we do ?
    Than in advance.
    Rgds
    --------------------
    PROCESS(reset, a, pcs2) --PROCESS no 2
    BEGIN
    IF reset = '0' THEN
    RDI <= (OTHERS => '0') ;
    PDI <= (OTHERS => '0') ;
    ELSIF pcs2 = '0' AND a = "00000" THEN
    RDI(7 DOWNTO 0) <= D ;
    ELSIF pcs2 = '0' AND a = "00001" THEN
    RDI(15 DOWNTO 8) <= D ;
    ELSIF pcs2 = '0' AND a = "00010" THEN
    RDI(23 DOWNTO 16)<= D ;
    ELSIF pcs2 = '0' AND a = "00011" THEN
    RDI(29 DOWNTO 24)<= D(5 DOWNTO 0) ;
    ELSIF pcs2 = '0' AND a = "00100" THEN
    PDI(7 DOWNTO 0) <= D ;
    ELSIF pcs2 = '0' AND a = "00101" THEN
    PDI(15 DOWNTO 8) <= D ;
    ELSIF pcs2 = '0' AND a = "00110" THEN
    PDI(23 DOWNTO 16)<= D ;
    ELSIF pcs2 = '0' AND a = "00111" THEN
    PDI(29 DOWNTO 24)<= D(5 DOWNTO 0) ;
    END IF ;
    END PROCESS ;
    ------------------------
    aaaaaa, May 5, 2005
    #1
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  2. aaaaaa wrote:


    > RDI output signals are not being latched .


    They /are/ latched! You did not assign every bit of RDI and PDI in any case.


    > At reset '0' , all signals
    > become low but as soon as reset becomes high , all RDI outputs become
    > high. and after that they are being latched properly.


    Do you talk about simulation of the behavioral or the netlist?

    If you talk about netlist simulation then it seems to be the "muxed
    latch problem": If there is a mux before a latch and one signal controls
    the latch and the mux it may be, that while the latch is beeing closed
    the mux changes the output sooner and the new value is loaded into the
    latch before it is finally disabled.


    > Pl suggest what should we do ?


    Did you think about the difficulties that arise while using latches?
    Latches are nice, small and power saving, but you have to design them
    carefully.
    If latches are preferrable for your task, control the mux with a
    different signal than the latch-enable. Hold the mux-output stable until
    the latch is closed.
    Otherwise think about using flipflops.

    Ralf
    Ralf Hildebrandt, May 5, 2005
    #2
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  3. aaaaaa

    Jim George Guest

    Ralf Hildebrandt wrote:
    > aaaaaa wrote:
    >
    >
    >> RDI output signals are not being latched .

    >
    >
    > They /are/ latched! You did not assign every bit of RDI and PDI in any
    > case.
    >
    >
    >> At reset '0' , all signals
    >> become low but as soon as reset becomes high , all RDI outputs become
    >> high. and after that they are being latched properly.

    >
    >
    > Do you talk about simulation of the behavioral or the netlist?
    >
    > If you talk about netlist simulation then it seems to be the "muxed
    > latch problem": If there is a mux before a latch and one signal controls
    > the latch and the mux it may be, that while the latch is beeing closed
    > the mux changes the output sooner and the new value is loaded into the
    > latch before it is finally disabled.
    >
    >
    >> Pl suggest what should we do ?

    >
    >
    > Did you think about the difficulties that arise while using latches?
    > Latches are nice, small and power saving, but you have to design them
    > carefully.
    > If latches are preferrable for your task, control the mux with a
    > different signal than the latch-enable. Hold the mux-output stable until
    > the latch is closed.
    > Otherwise think about using flipflops.
    >
    > Ralf


    The biggest problem with latches is during timing analysis, they are
    difficult to analyze because they have both a sequential and a
    combinatorial path. AFAIK, utilities like Xilinx TRCE will ignore the
    sequential path and report only the combinatorial path. This will make
    that path look like it has lots prop delay.
    Jim George, May 6, 2005
    #3
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