latches

[Runar Gjelsvik]

When I design state-machines I always get a lot of latches. I don't know how
to get rid of these, I've tried my best in several different ways to make
the combinatorial process complete but without luck. I've go this state
machine here with all these warnings:

WARNING:Xst:737 - Found 2-bit latch for signal <address>.
WARNING:Xst:737 - Found 88-bit latch for signal <dataFrame>.
WARNING:Xst:737 - Found 2-bit latch for signal <prefix>.
WARNING:Xst:737 - Found 32-bit latch for signal <rcvData>.
WARNING:Xst:737 - Found 1-bit latch for signal <frameLoaded>.
WARNING:Xst:1291 - FF/Latch <rcvData_31> is unconnected in block
<data_sorter>.
WARNING:Xst:1291 - FF/Latch <rcvData_30> is unconnected in block
<data_sorter>.


load_data:Block

type STATE_TYPE is (IDLE, STORE, DISTRIB, RESET);

attribute ENUM_ENCODING: STRING;
attribute ENUM_ENCODING of STATE_TYPE: type is "0001 0010 0100 1000";

signal CS, NS: STATE_TYPE;
signal rcvData : std_logic_vector(31 downto 0);
signal prefix : unsigned(1 downto 0);
signal address : integer range 0 to 3;

begin

SYNC_PROC: process (clk, rst)
begin
if (rst='1') then
CS <= RESET;
elsif (clk'event and clk = '1') then
CS <= NS;
end if;
end process;

COMB_PROC: process (CS, loadData, dataIn, data(0), data(1), data(2),
prefix, rcvData)
begin
case CS is
when IDLE => if loadData = '1' then
frameLoaded <= '0';
rcvData <= dataIn;
prefix <= unsigned(dataIn(31 downto 30));
NS <= STORE;
end if;
when STORE =>
address <= to_integer(prefix);
case prefix is
when "00" => data(address) <= rcvData;
NS <= IDLE;
when "01" => data(address) <= rcvData;
NS <= IDLE;
when "10" => data(address) <= rcvData;
NS <= DISTRIB;
when others => NS <= RESET;
end case;

when DISTRIB =>
dataFrame <= (data(2)(27 downto 0) & data(1)(29 downto 0) & data(0)(29
downto 0));
frameLoaded <= '1';
NS <= IDLE;

when RESET => for i in 0 to 2 loop
data(i) <= (others => '0');
end loop;
dataFrame <= (others => '0');
rcvData <= (others => '0');
frameLoaded <= '0';
prefix <= (others => '0');
NS <= IDLE;
when others => NS <= RESET;
end case;
end process;
end block;

 

[Egbert Molenkamp]

In the CASE statement you do not assign to address in all branches.
In state IDLE you do not assign to address; this means that the value of
address is remains its current value ==> your latch!

If you model a combinational circuit be sure to assign to a signal in all
branches.
In case the value of address is NOT important in the branches where do did
not assign to it you could consider assigning to address (and similar
signals) a value just before the case. Something like:

address <= "--"; -- any value is good
case CS is
...

Egbert Molenkamp

 

[Mike Treseler]

When I design state-machines I always get a lot of latches. I don't know
how to get rid of these, I've tried my best in several different ways to
make the combinatorial process complete but without luck. I've go this
state machine here with all these warnings:

Consider using a single synchronous process
for your controller.

-- Mike Treseler

 

[Ron]

If you dont have an else statement in your if statement you could end
up with a latch like in your case.

 

[caro_22]

Hi,

I have the following code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Roteren is
port
( keyin :in std_logic_vector(1 to 28 );
rondenr: in std_logic_vector(1 to 4);
E_D: in std_logic; -- Encryptie = 0 => links roteren --- Decryptie = 1 => rechts roteren
kuit : out std_logic_vector(1 to 28 )
);
end Roteren;

architecture Behavioral of Roteren is

component Roteer1 is
port
(
regin : in std_logic_vector(1 to 28 );
regout : out std_logic_vector(1 to 28 )
);
end component;

component Roteer1_right is port
(
regin : in std_logic_vector(1 to 28 );
regout : out std_logic_vector(1 to 28 )
);
end component;

component roteer2 is
port (
regin : in std_logic_vector(1 to 28 );
regout : out std_logic_vector(1 to 28 )
);
end component;

component roteer2_right is
port (
regin : in std_logic_vector(1 to 28 );
regout : out std_logic_vector(1 to 28 )
);
end component;

signal regin1left,regin2left : std_logic_vector(1 to 28 );
signal regout1left,regout2left : std_logic_vector(1 to 28 );
signal regin1right,regin2right : std_logic_vector(1 to 28 );
signal regout1right,regout2right : std_logic_vector(1 to 28 );

begin

roteer_1 : roteer1
port map(regin1left,regout1left);

roteer_2 : roteer2
port map(regin2left,regout2left);

roteer_1_right : roteer1_right
port map(regin1right,regout1right);

roteer_2_right : roteer2_right
port map(regin2right,regout2right);




process(E_D,keyin,rondenr,regout1left,regout2left,regout1right,regout2right)
begin
if (E_D = '0' and (rondenr = "0000" or rondenr = "0001" or rondenr = "1000" or rondenr = "1111")) then -- = ENCRYPTIE
regin1left <= keyin;
regin2left <= regin2left;
kuit <= regout1left;
elsif (E_D = '0') then
regin2left <= keyin;
regin1left <= regin1left;
kuit <= regout2left;
elsif (E_D = '1' and rondenr = "0000") then
kuit <= keyin;
regin2left <= regin2left;
elsif (E_D = '1' and (rondenr = "0001" or rondenr = "1000" or rondenr = "1111")) then
regin1right <= keyin;
regin2left <= regin2left;
kuit <= regout1right;
elsif (E_D = '1') then
regin2right <= keyin;
kuit <= regout2right;
regin2left <= regin2left;
else
regin2left <= regin2left;
end if;

end process;


end Behavioral;

But I get the warnings:

WARNING:Xst:737 - Found 28-bit latch for signal <regin1left>.
WARNING:Xst:737 - Found 28-bit latch for signal <regin2left>.
WARNING:Xst:737 - Found 28-bit latch for signal <regin1right>.
WARNING:Xst:737 - Found 28-bit latch for signal <regin2right>.

What is wrong with the code..???

Greetz,
Caro_22