library path problem

Discussion in 'VHDL' started by AG, Aug 1, 2007.

  1. AG

    AG Guest

    Hi all,

    I have the following type of code :

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_ARITH.ALL;
    LIBRARY mylib;
    USE mylib.ioport.ALL;


    ENTITY test IS
    PORT(
    clk : IN STD_LOGIC;
    rst : IN STD_LOGIC;
    A : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
    C : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
    );
    END test;

    ARCHITECTURE Solution_1 OF test IS
    SIGNAL A_1 : STD_LOGIC_VECTOR (11 DOWNTO 0);
    SIGNAL A_wire_z : STD_LOGIC_VECTOR (11 DOWNTO 0);
    BEGIN

    A_wire : mylib.ioport.wire
    GENERIC MAP(
    rscid => 1,
    width => 12
    )
    PORT MAP(
    d => A_1,
    z => A_wire_z
    );
    etc...
    END Solution_1;

    When I compile this with Xilinx ISE, the compiler stops at the line below
    this line :

    A_wire : mylib.ioport.wire

    with the following message :

    ERROR:HDLParsers:164 - "C:/temp/XST/test/mytest.vhdl" Line 245. parse error,
    unexpected GENERIC, expecting OPENPAR or TICK or LSQBRACK

    and if write instead :

    A_wire : wire

    the compiler stays quiet. I did not had this kind of problem with Quartus
    compiler. Who is wrong ? Is there somewhere an option that I can set so that
    I don't need to change the code everywhere this happens (and it does often
    in my code) ?

    Alexandre.
    AG, Aug 1, 2007
    #1
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  2. AG

    Andy Guest

    On Aug 1, 2:44 am, "AG" <> wrote:
    > Hi all,
    >
    > I have the following type of code :
    >
    > LIBRARY IEEE;
    > USE IEEE.STD_LOGIC_1164.ALL;
    > USE IEEE.STD_LOGIC_ARITH.ALL;
    > LIBRARY mylib;
    > USE mylib.ioport.ALL;
    >
    > ENTITY test IS
    > PORT(
    > clk : IN STD_LOGIC;
    > rst : IN STD_LOGIC;
    > A : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    > B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
    > C : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
    > );
    > END test;
    >
    > ARCHITECTURE Solution_1 OF test IS
    > SIGNAL A_1 : STD_LOGIC_VECTOR (11 DOWNTO 0);
    > SIGNAL A_wire_z : STD_LOGIC_VECTOR (11 DOWNTO 0);
    > BEGIN
    >
    > A_wire : mylib.ioport.wire
    > GENERIC MAP(
    > rscid => 1,
    > width => 12
    > )
    > PORT MAP(
    > d => A_1,
    > z => A_wire_z
    > );
    > etc...
    > END Solution_1;
    >
    > When I compile this with Xilinx ISE, the compiler stops at the line below
    > this line :
    >
    > A_wire : mylib.ioport.wire
    >
    > with the following message :
    >
    > ERROR:HDLParsers:164 - "C:/temp/XST/test/mytest.vhdl" Line 245. parse error,
    > unexpected GENERIC, expecting OPENPAR or TICK or LSQBRACK
    >
    > and if write instead :
    >
    > A_wire : wire
    >
    > the compiler stays quiet. I did not had this kind of problem with Quartus
    > compiler. Who is wrong ? Is there somewhere an option that I can set so that
    > I don't need to change the code everywhere this happens (and it does often
    > in my code) ?
    >
    > Alexandre.


    I think ISE is in the wrong. The prefixed name is not incorrect, but
    it is also not necessary, since you have made all objects (including
    components) in the package ioport compiled in the library mylib
    visible. I would remove either the prefix or the use statement, but
    both are not necessary. On the other hand, they are not erroneous
    either.

    You could also just instantiate the entity/architecture directly, and
    dispense with the component altogether, but there are still visibility/
    prefix rules that have to be obeyed. Almost the only time I use a
    component is when I'm instantiating a primitive that the synthesis
    tool recognizes, yet it needs to be bound to an entity/architecture
    for simulation.

    Andy
    Andy, Aug 1, 2007
    #2
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  3. AG

    JK Guest

    On Aug 1, 12:44 pm, "AG" <> wrote:
    >
    > A_wire : mylib.ioport.wire
    > GENERIC MAP(
    > rscid => 1,
    > width => 12
    > )
    > PORT MAP(
    > d => A_1,
    > z => A_wire_z
    > );
    > etc...
    > END Solution_1;
    >


    Is wire entity name?
    Have you tried putting entity before library like this...

    A_wire : entity mylib.ioport.wire
    GENERIC MAP(
    rscid => 1,
    width => 12
    )
    PORT MAP(
    d => A_1,
    z => A_wire_z
    );

    for more information:
    http://groups.google.com/group/comp...68?lnk=st&q=component&rnum=5#2edf789a0474c768

    Regards,
    JK
    JK, Aug 2, 2007
    #3
  4. AG

    AG Guest

    > Is wire entity name?
    No it is a component name.

    > Have you tried putting entity before library like this...
    >
    > A_wire : entity mylib.ioport.wire
    > GENERIC MAP(
    > rscid => 1,
    > width => 12
    > )
    > PORT MAP(
    > d => A_1,
    > z => A_wire_z
    > );

    yes, I tried it this morning, but as it is a component name, the compiler is
    asking for an entity name.

    > for more information:
    > http://groups.google.com/group/comp...68?lnk=st&q=component&rnum=5#2edf789a0474c768

    Thank you for this.
    AG, Aug 2, 2007
    #4
  5. AG

    AG Guest


    > I think ISE is in the wrong. The prefixed name is not incorrect, but
    > it is also not necessary, since you have made all objects (including
    > components) in the package ioport compiled in the library mylib
    > visible. I would remove either the prefix or the use statement, but
    > both are not necessary. On the other hand, they are not erroneous
    > either.

    I tried to remove the use statement, but it did not changed anything. (Note
    that wire is a component name)
    By removing the prefix, it works well.


    > You could also just instantiate the entity/architecture directly, and
    > dispense with the component altogether, but there are still visibility/
    > prefix rules that have to be obeyed. Almost the only time I use a
    > component is when I'm instantiating a primitive that the synthesis
    > tool recognizes, yet it needs to be bound to an entity/architecture
    > for simulation.

    The code is automatically written, so I can't really change anything, except
    afterwards by removing the prefix with the script eventually :-(

    AG.
    AG, Aug 2, 2007
    #5
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