Library woes switching between ModelSim and Xilinx ISE

Discussion in 'VHDL' started by Garrick, Aug 15, 2006.

  1. Garrick

    Garrick Guest

    I'm having an issue with simulation of Xilinx Coregen'ed entities. The
    FIFO I'm simulating and including in my ISE project compiles and works
    in both, but I can't get the FIFO behavioral file/model to be bound
    properly in ModelSim from the Work library, which requires compiling
    and maping it from a seperate library (which in turn troubles Xilinx
    ISE).

    So, right now, I have:
    1. FIFO1.xco in ISE, which generates FIFO1.vhd for behavioral
    simulation.
    2. mycode.vhd, which has a componet FIFO1 declaration in it's
    architecture , and fifoA : FIFO1 port map etc.

    In my modelsim compilation script, I would like to:
    vcom -93 -work work fifo1.vhd

    and have the FIFO entity bound in properly. I can see the entity in
    the Work library with all my other entities, but I get a "** Warning:
    (vsim-3473) Component 'fifoA' is not bound when starting simulation.

    So, to get this to simulate, I've added the following to mycode.vhd:
    library myFIFOs;
    use myFIFOs.all;

    and my modelsim script now contains:
    vlib myFIFOs
    vmap myFIFOs myFIFOs
    vcom -93 -work okFIFOs fifo1.vhd

    This works. The FIFO is bound properly and simulation is great.
    However, when switching back to ISE, I have to comment out the the
    myFIFOs library links above. This is annoying and seemingly
    unnecessary (I have a lot of cores to use like this).

    What am I doing wrong? What's the cleanest trick to get my FIFO
    behaviorial file to bind properly in ModelSim while maintaining the
    same top level file between ISE and ModelSim?

    Thank you, Garrick.
    Garrick, Aug 15, 2006
    #1
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  2. Garrick

    backhus Guest

    Garrick schrieb:
    > I'm having an issue with simulation of Xilinx Coregen'ed entities. The
    > FIFO I'm simulating and including in my ISE project compiles and works
    > in both, but I can't get the FIFO behavioral file/model to be bound
    > properly in ModelSim from the Work library, which requires compiling
    > and maping it from a seperate library (which in turn troubles Xilinx
    > ISE).
    >
    > So, right now, I have:
    > 1. FIFO1.xco in ISE, which generates FIFO1.vhd for behavioral
    > simulation.
    > 2. mycode.vhd, which has a componet FIFO1 declaration in it's
    > architecture , and fifoA : FIFO1 port map etc.
    >
    > In my modelsim compilation script, I would like to:
    > vcom -93 -work work fifo1.vhd
    >
    > and have the FIFO entity bound in properly. I can see the entity in
    > the Work library with all my other entities, but I get a "** Warning:
    > (vsim-3473) Component 'fifoA' is not bound when starting simulation.
    >
    > So, to get this to simulate, I've added the following to mycode.vhd:
    > library myFIFOs;
    > use myFIFOs.all;
    >
    > and my modelsim script now contains:
    > vlib myFIFOs
    > vmap myFIFOs myFIFOs
    > vcom -93 -work okFIFOs fifo1.vhd
    >
    > This works. The FIFO is bound properly and simulation is great.
    > However, when switching back to ISE, I have to comment out the the
    > myFIFOs library links above. This is annoying and seemingly
    > unnecessary (I have a lot of cores to use like this).
    >
    > What am I doing wrong? What's the cleanest trick to get my FIFO
    > behaviorial file to bind properly in ModelSim while maintaining the
    > same top level file between ISE and ModelSim?
    >
    > Thank you, Garrick.
    >

    Hi Garric
    how about using the XilinxCorelib?

    vmap xilinxcorelib <path_to_xilinxcorelib)

    Compiling fifo1.vhd to work is ok, and should work.

    It's not neccessary to put the library myFIFOs into your code.

    > vcom -93 -work okFIFOs fifo1.vhd

    okFIFOs is a typing error, isn't it?

    Are you using configurations in mycode.vhd?
    If so you may need to include the configuration for FIFO1 rather than
    the entity.

    ....
    for fifoA: use configuration work.FIFO1
    ....

    have a nice simulation
    Eilert
    backhus, Aug 16, 2006
    #2
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  3. On 15 Aug 2006 11:02:20 -0700, "Garrick" <> wrote:

    >I'm having an issue with simulation of Xilinx Coregen'ed entities. The
    >FIFO I'm simulating and including in my ISE project compiles and works
    >in both, but I can't get the FIFO behavioral file/model to be bound
    >properly in ModelSim from the Work library, which requires compiling
    >and maping it from a seperate library (which in turn troubles Xilinx
    >ISE).


    >So, to get this to simulate, I've added the following to mycode.vhd:
    >library myFIFOs;
    >use myFIFOs.all;


    >However, when switching back to ISE, I have to comment out the the
    >myFIFOs library links above. This is annoying and seemingly
    >unnecessary (I have a lot of cores to use like this).


    The library/use clauses can be guarded by pragmas

    -- pragma translate_off
    library myFIFOs;
    use myFIFOs.all;
    -- pragma translate_on

    which (or some similar syntax) are understood by synthesis tools
    including ISE, but are ignored by simulation. So simulation sees the
    library/use clause, but synthesis does not.

    - Brian
    Brian Drummond, Aug 16, 2006
    #3
  4. Garrick

    Duane Clark Guest

    Garrick wrote:
    > I'm having an issue with simulation of Xilinx Coregen'ed entities. The
    > FIFO I'm simulating and including in my ISE project compiles and works
    > in both, but I can't get the FIFO behavioral file/model to be bound
    > properly in ModelSim from the Work library, which requires compiling
    > and maping it from a seperate library (which in turn troubles Xilinx
    > ISE).
    >
    > So, right now, I have:
    > 1. FIFO1.xco in ISE, which generates FIFO1.vhd for behavioral
    > simulation.
    > 2. mycode.vhd, which has a componet FIFO1 declaration in it's
    > architecture , and fifoA : FIFO1 port map etc.
    >
    > In my modelsim compilation script, I would like to:
    > vcom -93 -work work fifo1.vhd
    >
    > and have the FIFO entity bound in properly. I can see the entity in
    > the Work library with all my other entities, but I get a "** Warning:
    > (vsim-3473) Component 'fifoA' is not bound when starting simulation.


    Perhaps you should show mycode.vhd for this version. The description you
    have given should work, so you have made a mistake somewhere. Without
    seeing what you have done, it is hard to figure out where the problem
    is. The following works fine with the steps you have given:


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    ENTITY mycode IS
    port (
    clk: IN std_logic;
    din: IN std_logic_VECTOR(15 downto 0);
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
    END mycode;

    ARCHITECTURE synth OF mycode IS
    component fifo1
    port (
    clk: IN std_logic;
    din: IN std_logic_VECTOR(15 downto 0);
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
    end component;
    begin

    fifoA : FIFO1
    port map (
    clk => clk,
    din => din,
    rd_en => rd_en,
    rst => rst,
    wr_en => wr_en,
    dout => dout,
    empty => empty,
    full => full);

    end architecture synth;
    Duane Clark, Aug 16, 2006
    #4
  5. Garrick

    Garrick Guest

    Thank you all for the excellent replies. Each of you gave me something
    different to think about.

    backhus wrote:
    > Compiling fifo1.vhd to work is ok, and should work.
    >
    > It's not neccessary to put the library myFIFOs into your code.


    Eilert and Duane seem to think it should have worked, so I'll show more
    source per Duane's request. BTW, the FIFO resides in an OPB peripheral
    for a Xilinx EDK MicroBlaze design so there are multiple layers of
    crap. The "mycode.vhd" is a sub-file of the peripheral:

    mycode.vhd: ------------------------------
    library ieee;
    use ieee.std_logic_1164.all;

    entity user_logic is
    port (
    Bus2IP_Clk : in std_logic;
    Bus2IP_Reset : in std_logic;
    IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1);
    Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
    ...
    IP2Bus_AddrAck : out std_logic
    );
    end entity user_logic;

    architecture IMP of user_logic is
    ...
    component fifo16x1024_to_32x512 port (
    din : in std_logic_vector(15 downto 0);
    rd_clk : in std_logic;
    rd_en : in std_logic;
    rst : in std_logic;
    wr_clk : in std_logic;
    wr_en : in std_logic;
    dout : out std_logic_vector(31 downto 0);
    empty : out std_logic;
    full : out std_logic;
    rd_data_count : out std_logic_vector(8 downto 0));
    end component;
    ...

    begin
    ....

    fifoIn : fifo16x1024_to_32x512 port map (
    rst => Bus2IP_Reset, wr_clk => ti_clk, wr_en => pipeInWrite,
    din => pipeInData, rd_clk => Bus2IP_Clk, rd_en => pipeInRead,
    dout => pipeInDout, rd_data_count => pipeInRdStatus, full =>
    pipeInFull,
    empty => pipeInEmpty);
    end IMP;
    -----------------------------

    backhus wrote:
    > > vcom -93 -work okFIFOs fifo1.vhd

    > okFIFOs is a typing error, isn't it?


    No, actually for simulation I have at the top of my code above:
    library okFIFOs;
    use okFIFOs.all;

    And my ModelSim do file contains:
    vlib okFIFOs
    vmap okFIFOs okFIFOs
    vcom -93 -work okFIFOs fifo1.vhd # fifo1.vhd contains behavioral
    # entity of fifo16x1024_to_32x512

    Is this vcom "style" odd? To make a "work" library called okFIFOs? I
    adopted this system in my compilation do file from the Xilinx Platform
    Studio EDK. It outputs large do files that incorporate all the
    wrappers necessary for simulation. I just modified their script to
    include libraries necessary for my peripheral and test fixture. In any
    case, it works very well so far.

    *** What still doesn't work is commenting out the library/use okFIFOs
    declaration in mycode.vhd and having my do file just contain:
    vcom -93 -work work fifo1.vhd

    I know this seems wrong and I must be doing something wrong. When I do
    this I can see the fifo16x1024_to_32x512 entity along with everything
    else in my work library in ModelSim. It just doesn't bind!

    backhus wrote:
    > how about using the XilinxCorelib?


    XilinxCoreLib is necessary for entities inside the toplevel
    fifo16x1024_to_32x512 entity and other code as well. It is already
    included in the compilation do file:
    vmap XilinxCoreLib
    C:/Installed/XilinxSimLib/EDK8.1_mti_se_nt/ISE_Lib/XilinxCoreLib/

    and is linked into my simulation:
    vsim -L unisim -L XilinxCoreLib -t ps tb_conf

    Did you mean to try compiling my FIFO behavioral model into
    XilinxCoreLib?

    Brian Drummond wrote:
    > -- pragma translate_off
    > library myFIFOs;
    > use myFIFOs.all;
    > -- pragma translate_on


    This works great! However, I still want to figure out what I'm doing
    wrong above.

    Thank you all for your time and suggestions,

    Garrick
    Garrick, Aug 17, 2006
    #5
  6. Garrick

    Duane Clark Guest

    So I created a core with the identical IO pins as yours, and with the
    same name. I copied to where I did the rest of the project.

    I created mycode.vhd that looks exactly like what you have, except that
    I remove the ellipses and change the entity to look like:

    entity user_logic is
    port (
    pipeInData : in std_logic_vector(15 downto 0);
    Bus2IP_Clk : in std_logic;
    pipeInRead : in std_logic;
    Bus2IP_Reset : in std_logic;
    ti_clk : in std_logic;
    pipeInWrite : in std_logic;
    pipeInDout : out std_logic_vector(31 downto 0);
    pipeInEmpty : out std_logic;
    pipeInFull : out std_logic;
    pipeInRdStatus : out std_logic_vector(8 downto 0)
    );
    end entity user_logic;

    I created a project mpf file that contains the library mappings:
    unisim = $XILINX/vhdl/src/unisims/work
    XilinxCoreLib = $XILINX/vhdl/src/XilinxCoreLib/work

    I created a testbench file that looks like:

    library IEEE;
    use IEEE.std_logic_1164.all;

    entity bd_top is
    end entity bd_top;

    architecture board of bd_top is
    constant CLK_PRD : Time := 20 ns;

    signal CLK : std_logic;
    signal RST : std_logic;
    begin
    UUT: entity work.user_logic
    port map(
    pipeInData => X"0000",
    Bus2IP_Clk => CLK,
    pipeInRead => '0',
    Bus2IP_Reset => RST,
    ti_clk => CLK,
    pipeInWrite => '0',
    pipeInDout => open,
    pipeInEmpty => open,
    pipeInFull => open,
    pipeInRdStatus => open
    );

    RST <= '1', '0' after 100 nS;

    clk_gen: process is
    begin
    wait for 6 ns;
    loop
    CLK <= '1' after CLK_PRD/2, '0' after CLK_PRD;
    wait for CLK_PRD;
    end loop;
    end process clk_gen ;

    end architecture board;


    I executed:
    vlib work
    vcom -93 -work work fifo16x1024_to_32x512.vhd
    vcom -93 -work work mycode.vhd
    vcom -93 -work work bd_top.vhd
    (normally I don't bother typing the "-93 -work work", since the work
    library is implied and my mpf file contains "VHDL93 = 1")

    I then ran vsim, opened bd_top, and ran a simulation. The transcript
    file generated shows:
    # vsim work.bd_top
    # ...
    # Loading /opt/modeltech/linux/../std.standard
    # Loading /opt/modeltech/linux/../ieee.std_logic_1164(body)
    # Loading work.bd_top(board)
    # Loading work.user_logic(imp)
    # Loading
    /opt/Xilinx8.2/vhdl/src/XilinxCoreLib/work.iputils_std_logic_arith(body)
    # Loading
    /opt/Xilinx8.2/vhdl/src/XilinxCoreLib/work.iputils_std_logic_unsigned(body)
    # Loading /opt/modeltech/linux/../std.textio(body)
    # Loading /opt/Xilinx8.2/vhdl/src/XilinxCoreLib/work.iputils_conv(body)
    # Loading /opt/Xilinx8.2/vhdl/src/XilinxCoreLib/work.iputils_misc(body)
    # Loading work.fifo16x1024_to_32x512(fifo16x1024_to_32x512_a)
    # Loading
    /opt/Xilinx8.2/vhdl/src/XilinxCoreLib/work.fifo_generator_v2_3(behavioral)
    # Loading
    /opt/Xilinx8.2/vhdl/src/XilinxCoreLib/work.fifo_generator_v2_3_bhv_as(behavioral)
    view signals
    # .signals
    view wave
    # .wave
    view structure
    # .structure
    run 20000000

    Can you duplicate those steps? That should only take about 10 minutes.
    Duane Clark, Aug 18, 2006
    #6
  7. Garrick

    lolita

    Joined:
    Apr 6, 2009
    Messages:
    3
    help

    hi
    i want to ask, what does library in ISE xilinx do?
    and, how i can to create it?
    i try to synthetase a full description of a SoC and i have a lot problems of library.:-(

    please help me!! :oops:


    lolita
    lolita, Apr 8, 2009
    #7
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