link betwen signal vhdl bench and entity (quartus2&modelsim)

Discussion in 'VHDL' started by picnanard, Mar 7, 2007.

  1. picnanard

    picnanard

    Joined:
    Mar 5, 2007
    Messages:
    19
    Hello,

    i have two vhdl prog
    FIFO(RTL)
    entity2(arch2)

    I see these programs in project windows of quartus 2.

    i have another prog bench in vhdl
    this vhdl bench is aimed by quartus in tool-simulation-bench
    The software simulation is modelsim altera

    when can i make a link betwen the signal (vhdl bench )
    and the in/out of entitys

    In bench vhdl i try :
    LED_FIFO : FIFO use entity work.FIFO(RTL);
    HED_FIFO : FIFO use entity work.FIFO(RTL);
    LED_fifo: map(
    link
    in/out=>signal
    )

    quartus don't find component FIFO.

    Please help.
    Thanks
     
    picnanard, Mar 7, 2007
    #1
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