linking readable port names with indexed array

Discussion in 'VHDL' started by mdearman, Sep 17, 2009.

  1. mdearman

    mdearman

    Joined:
    Sep 17, 2009
    Messages:
    1
    I have a design which has a large number of bidirectional ports.

    Internally i want to refer to them as an array i.e control_pins(71 downto 0), but i want to use readable names at the port level, so that the pinout file is easy to read

    if the signals were unidirectional i could just individually assign everything, i.e

    SIGNAL_A <= control_pins(0)
    SIGNAL_C <= control_pins(1)

    but i can't do that because they're bidirectional and the assignment operator isn't.

    so another option might be to use aliases

    alias control_pins(0) is SIGNAL_A

    or

    alias SIGNAL_A is control_pins(0)

    neither of which are valid.

    am i missing something very obvious?

    thanks,

    Mike
     
    mdearman, Sep 17, 2009
    #1
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