long/short sensitivity list

Discussion in 'VHDL' started by titi, Mar 6, 2007.

  1. titi

    titi Guest

    In the sample code here after, the sensitivity list is (Reset,Load,F).
    Would it be correct to write (Reset,F)?
    Why, why not?


    machin : process(Reset,Load,F)
    begin
    if Reset ='1' then
    En1 <= '0';
    En2 <= '0';
    elsif F'event and F ='1' then
    En1 <= Load;
    En2 <= En1;
    end if;
    end process;
    titi, Mar 6, 2007
    #1
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  2. titi

    KJ Guest

    "titi" <> wrote in message
    news:esjgpf$117t$...
    > In the sample code here after, the sensitivity list is (Reset,Load,F).
    > Would it be correct to write (Reset,F)?
    > Why, why not?
    >
    > machin : process(Reset,Load,F)
    > begin
    > if Reset ='1' then
    > En1 <= '0';
    > En2 <= '0';
    > elsif F'event and F ='1' then
    > En1 <= Load;
    > En2 <= En1;
    > end if;
    > end process;


    The correct sensitivity list is "Reset, F". The reason is because nothing
    happens when the signal "Load" changes (as you have in your list). To see
    for yourself, simply take a walk through the code holding all inputs
    constant and you'll see that the only way you can get to the lines
    > En1 <= Load;
    > En2 <= En1;

    are if there has been a rising edge detected on signal 'F'. So change
    'Load' all that you want all by itself and it will not affect the outputs of
    the process 'En1' and 'En2'. By adding 'Load' to the sensitivity list,
    you're telling the simulator to execute this process whenever 'Load'
    changes. But as you've seen, none of the outputs will change as a result of
    a change in 'Load' so you've caused the simulator to needlessly waste cycles
    evaluating something for no reason.

    On the plus side, there are much worse things than wasting CPU cycles, the
    design as written will simulate and synthesize just fine. There are much
    worse things. Ask yourself what would happen if you left 'Reset' out of the
    sensitivity list instead (by accident). In that situation, the asynchronous
    resetting of 'En1' and 'En2' would not occur. If your clock signal 'F'
    happens to be running while 'Reset' is true then the resetting will occur at
    the next rising edge of 'F' (i.e. a synchronous reset) but if it's not then
    the code after 'if Reset='1' then...' will never execute. Most any
    synthesis tool will report this as a warning about an incomplete sensitivity
    list and will implement what you intended AS IF you had included 'Reset' in
    the sensitivity list. Things like this cause simulation results and actual
    implementation results to differ.

    I'll also take a moment to encourage the use of
    if rising_edge(F) then...
    as being clearer than
    if F'event and F ='1' then

    Kevin Jennings
    KJ, Mar 6, 2007
    #2
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