Loop in procedure not complete

[ALuPin]

Hi,

I am trying to monitor the loop index within a procedure in a VHDL
testbench as follows:



procedure test (signal Clock : std_logic;
Times : integer;
signal Data : std_logic_vector(7 downto 0) ) is

variable wait_index : integer;
variable i : integer;
variable j_help : integer;
variable ln : line;
begin

wait_index := Times;

LOOP1_OUT : for i in 0 to 15000 loop
j_help := i;

if (i <= wait_index) then
if i=wait_index then
writeline(OUTPUT,ln);
write(ln,string'("loop "));
write(ln,j_help);
end if;
wait on Clock, Data;
exit LOOP1_OUT when Data="10000100";
end if;

end loop;

end test;

-- Calling procedure within main process
process
begin
test(t_Clock, 50, t_Data);

wait;
end process;

I get no monitoring in Modelsim at all. Why?
("Data" remains "00000000" all the time so that no
loop exit comes into question)

When I comment the inner if-statement out
if (i <= wait_index) then
--if i=wait_index then
writeline(OUTPUT,ln);
write(ln,string'("loop "));
write(ln,j_help);
--end if;
wait on Clock, Data;
exit LOOP1_OUT when Data="10000100";
end if;

I get monitored in Modelsim
loop 0
loop 1
....
loop 49

But loop 50 is missing. Why?

Changings to
writeline(OUTPUT,ln);
write(ln,string'("loop "));
write(ln,i);
do not change anything.

Thank you for your help.

Rgds
André

 

[Jonathan Bromley]

When I comment the inner if-statement out
if (i <= wait_index) then
--if i=wait_index then
writeline(OUTPUT,ln);
write(ln,string'("loop "));
write(ln,j_help);
--end if;
wait on Clock, Data;
exit LOOP1_OUT when Data="10000100";
end if;

I get monitored in Modelsim
loop 0
loop 1
...
loop 49

But loop 50 is missing. Why?

Try moving the writeline() call to AFTER the two
write() calls, so that your message from the final
iteration is indeed written to stdout

And for further credit: explain why your original
code exhibits a memory leak.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[ALuPin]

I have found some post on the topic "writeline VHDL"

Write and Writeline are fuctions defined in the STD.TEXTIO >library of VHDL.

Line is a type def. It is access STRING. i.e it is a pointer
to a STRING.

Fn. Write adds the string specfd. to this Line (in Ur case strbuf).

Writeline Flushes this line onto the file specfd. (in Ur case
output).

\/
And from this the memory leak arises! Is that correct ?

 

[Jonathan Bromley]

library of VHDL.

\/
And from this the memory leak arises! Is that correct ?

Not quite.

Typically, a procedure that does text output will build up some
text in a LINE variable using WRITE() and then send it to a
file or the console using WRITELINE(). Each call to
WRITE(L, stuff)
allocates a little more memory, to accommodate the new text.
However, when you eventually do
WRITELINE(output, L)
the memory pointed-to by L is deallocated (returned to free store)
and L is reset to NULL. This is fine. There is no memory leak.

However, in your original code, you did some WRITE operations
without a final WRITELINE. Consequently, at the end of your
procedure, the line variable points to some memory that has been
allocated to your program. But then your procedure returns, the
line variable goes out of scope, and nothing points to the
memory any more! So the allocated memory is lost. Each time you
call the procedure, a little more memory is lost. There is a
memory leak.

Languages such as 'e' that do automatic garbage collection do
not suffer this problem, but of course they pay a price in
performance.

The correct solution is to be very sure that any local pointer
variables used in your procedure are deallocated before the
procedure returns. A procedure such as WRITELINE does the
deallocation automatically, but in some situations you must
do it for yourself.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[john Doef]

Jonathan Bromley a écrit :

Not quite.

Typically, a procedure that does text output will build up some
text in a LINE variable using WRITE() and then send it to a
file or the console using WRITELINE(). Each call to
WRITE(L, stuff)
allocates a little more memory, to accommodate the new text.
However, when you eventually do
WRITELINE(output, L)
the memory pointed-to by L is deallocated (returned to free store)
and L is reset to NULL. This is fine. There is no memory leak.

Huu, this is not what the LRM says.

LRM says:
Procedure WRITELINE causes the current line designated by parameter L
to be written to the file and returns with the value of parameter L
designating a null string.

If L designates a null string, it is not reset to NULL.

JD.

 

[Jonathan Bromley]

Jonathan Bromley a écrit : [...]

However, when you eventually do
WRITELINE(output, L)
the memory pointed-to by L is deallocated (returned to free store)
and L is reset to NULL. This is fine. There is no memory leak.

Huu, this is not what the LRM says.

LRM says:
Procedure WRITELINE causes the current line designated by parameter L
to be written to the file and returns with the value of parameter L
designating a null string.

If L designates a null string, it is not reset to NULL.

You're right, and I was careless. Sorry.

My point about the memory leak remains valid. But of course
there is an important difference: a LINE that designates a
null string has attributes such as 'LENGTH, but if you set
an access variable to NULL and then try to examine its
attributes you will get a bad-pointer error.

Thanks for the clarification.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.