Loop statement in VHDL

Discussion in 'VHDL' started by moranbendor, Oct 12, 2006.

  1. moranbendor

    moranbendor

    Joined:
    Oct 12, 2006
    Messages:
    1
    Hi,
    I'm trying to do a loop statement in VHDL ad follow:
    FOR i IN 0 TO ImageDataRegDepth LOOP
    DataShiftReg((i+1)*16 - 1 DOWNTO i*16) <= ImageDataRegArray(i);
    END LOOP;
    Is someone know why I can't do it ?
    How else can I do it ?
    moranbendor, Oct 12, 2006
    #1
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  2. moranbendor

    minombre

    Joined:
    Oct 2, 2008
    Messages:
    2
    for loop is secuential code so you have to execute it in a process. This is an example of a program (well hardware description) I was making

    process(entrada1)
    begin
    for i in 0 to 3
    loop
    t1(i)<=entrada1(i) and entrada2 (0)

    end loop;
    end process;

    Hope this helps:driver:
    minombre, Oct 2, 2008
    #2
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