Loosen timing on a net (xilinx)

Discussion in 'VHDL' started by rodentje, Mar 21, 2011.

  1. rodentje

    rodentje

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    Hi,

    I have a reset pulse "reset_clk1" generated on clock "clk1" which is held high for at least 16 clock cycles after a reset condition has occurred.

    This reset also resets a FIFO which is used to cross clock domains from clock domain "clk2" to "clk1".

    I want to loosen the timing from net "reset_clk1" to the resetting of the FIFO and some other nets (the FIFO is generated using coregen and has an asynchronous reset).

    I don't want to do this using a timing ignore (TIG), but I want to specify how much margin can be taken.

    How should I do this ?

    Best regards,
    RoDeNtJe
     
    rodentje, Mar 21, 2011
    #1
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