lpm_counter instead adders

Discussion in 'VHDL' started by Dan NITA, Mar 8, 2005.

  1. Dan NITA

    Dan NITA Guest

    Hi,

    When I using a plus-one adder or a minus-one adder inside a VHDL state
    machine, QuartusII integrated synthesis tools is unable to convert to an
    lpm_counter megafunction.

    Compilation report showed that instead lpm_counter it uses the adders and it
    cause the increase of the use of logic cells.

    There is a way to avoid adders?

    Thanks,

    Dan.
     
    Dan NITA, Mar 8, 2005
    #1
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  2. Dan NITA wrote:

    > When I using a plus-one adder or a minus-one adder inside a VHDL state
    > machine, QuartusII integrated synthesis tools is unable to convert to an
    > lpm_counter megafunction.


    That's a feature.
    You only need a megafunction if you
    prefer filling out a form to writing
    n := n + 1;
    Quartus synthesis is just filling out
    the form for you.

    > Compilation report showed that instead lpm_counter it uses the adders and it
    > cause the increase of the use of logic cells.


    You can't do much without using logic cell or two.

    > There is a way to avoid adders?


    You can't inc or dec your counter otherwise.

    -- Mike Treseler
     
    Mike Treseler, Mar 9, 2005
    #2
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  3. > Dan NITA wrote:
    >
    >> When I using a plus-one adder or a minus-one adder inside a VHDL state
    >> machine, QuartusII integrated synthesis tools is unable to convert to an
    >> lpm_counter megafunction.


    From www.altera.com (Find Answers) I found following code for an
    up/down-counter,
    let's hope it inferes the counter correctly, I have not tested it:

    ENTITY counters IS
    PORT( d : IN INTEGER RANGE 0 TO 255;
    clk : IN BIT;
    clear : IN BIT;
    load : IN BIT;
    up_down : IN BIT;
    qd : OUT INTEGER RANGE 0 TO 255);
    END counters;

    ARCHITECTURE a OF counters IS
    BEGIN
    -- An up/down counter
    PROCESS (clk)
    VARIABLE cnt : INTEGER RANGE 0 TO 255;
    VARIABLE direction : INTEGER;
    BEGIN
    IF (up_down = '1') THEN --Generate up/down counter
    direction := 1;
    ELSE
    direction := -1;
    END IF;
    IF (clk'EVENT AND clk = '1') THEN
    IF (load = '1') THEN --Generate loadable
    cnt := d; --counter. Take these
    ELSE --lines out to increase
    performance.
    cnt := cnt + direction;
    END IF;
    --The following lines will produce a synchronous
    --clear on the counter
    IF (clear = '0') THEN
    cnt := 0;
    END IF;
    END IF;
    qd <= cnt; --Generate outputs
    END PROCESS;
    END a;Infering does generally not always work correctly, in fact Ihave just
    today sent a mySupport service request because it doesnot infer a counter
    correctly, when a synchronuous set to valuesother than all 1's is used.Also
    I was not able to infer a true dual-port memory, while asimple dual-port-RAM
    (1 read, 1 write) did work.Let's hope for further
    improvement.Regards,Thomaswww.entner-electronics.comP.S.: I am using Outlook
    Express to read this newsgroup and I think that Imiss some posts?!? Is this
    due to Outlook, or is something else going on?
     
    Thomas Entner, Mar 9, 2005
    #3
  4. Thomas Entner wrote:
    > Infering does generally not always work correctly,


    There is "correctly(1)" meaning "what I meant it to do" and
    there is "correctly(2)" meaning "how the templated code actually simulates".

    Synthesis vendors are very good at correctly(2).

    > I was not able to infer a true dual-port memory, while asimple dual-port-RAM
    > (1 read, 1 write) did work.


    This is true for all vendors at the moment.
    However (1 read, 1 write) is all you need
    to make a fifo.

    -- Mike Treseler
     
    Mike Treseler, Mar 9, 2005
    #4
  5. Dan NITA

    Dan NITA Guest

    I finally found what is was wrong. In fact, my counter it was "spread" all
    over the state-machine. The counter load was implemented on the different
    state than the minus-one adder.
    To avoid that I used a variable to hold the preset value.
    .....
    when state1 =>
    varPreset := X"12345678";
    .....
    when state2 =>
    if (varCount(31) = '1') then
    varCount := varPreset;
    else
    varCount := varCount - 1;
    end if;
    .....
    when state3 =>
    .....

    The wrong way was:
    .....
    when state1 =>
    if (varCount(31) = '1') then
    varCount:= X"12345678";
    end if;
    .....
    when state2 =>
    varCount := varCount - 1;
    .....
    when state3 =>
    .....

    The most amazing is that even if I try to use varCount(31) outside state2,
    the interfering does not work correctly. The solution is to use another
    signal or variable to hold varCount(31) .

    Dan.
     
    Dan NITA, Mar 10, 2005
    #5
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