lvds signal in a stratix

Discussion in 'VHDL' started by bhb, Jul 1, 2003.

  1. bhb

    bhb Guest

    Hi all,

    I need to use a LVDS signal as a clock (in PLL) in a Stratix.
    Is someone could explain me how to implement this clk (in a csf file or
    in Quartus II with "assign pin") ?.

    Can you tell me if I need :
    to indicate 2 signals in my VHDL file :
    CLK_INn : in std_logic;
    CLK_INp: in std_logic;
    => how to simulate this clk_in with ModelSim (VHDL Script file)
    or only :
    CLK_IN : in std_logic;
    => how to indicate the two pin external number ?.

    Thanks lot for your answer.
    bhb.
     
    bhb, Jul 1, 2003
    #1
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