make: are command line variables stored in a macro?

Discussion in 'C Programming' started by Dave Programmer, Oct 19, 2007.

  1. In a Makefile, I have something like the following:

    # makefile start

    X = "default_x"
    Y = "default_y"

    targA:
    dosomething -x $(X) -y $(Y)

    targB:
    $(MAKE) targA X=newX

    #makefile end

    I'd like to be able to have the option to specify another value of Y
    on the command line when making targB and have that passed correctly
    to "dosomething"

    make targB Y=new_Y

    In fact, in my real makefile, I have several such variables I'd like
    to be able to modify on the command line. The only way I've been able
    to come up with to do this is to modify targB so

    targB:
    $(MAKE) targA X=newX Y=$(Y)

    but this gets unwieldy for several variables. Is there a better way to
    do this? Is there a Make macro in which command line variables/macros
    are stored?
    Dave Programmer, Oct 19, 2007
    #1
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  2. Dave Programmer

    Mark Bluemel Guest

    Dave Programmer wrote:
    > In a Makefile, I have something like the following:


    And your C question was what exactly?

    Your question is more likely to be on topic in comp.unix.programmer, I
    suspect.

    <Off-Topic>

    You could look at the manual for (your particular implementation of)
    "make" and see if the way it uses environment variables would help you

    But don't continue the discussion here, please.
    </Off-Topic>
    Mark Bluemel, Oct 19, 2007
    #2
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