Makefile with source code in 2 directory

[Rudra Banerjee]

Dear friends,
my project has structure like
$ls new
files Makefile help.c table.c callbk_list.h cwlst.h
where files is a directory, with hundreds of C code, which are the functions in the main code table.c

I tried to compile with Makefile as:
CC=gcc
CFLAGS =-O3
SUBDIR=files
PCONF1=pkg-config --cflags --libs gtk+-2.0
objects := $(wildcard $(SUBDIR)/*.o)
ptbl: $(objects) help.c table.c callbk_list.h cwlst.h
$(CC) `$(PCONF1)` $(objects) help.c table.c -o ptbl

$(SUBDIR)/%.o: $(SUBDIR)/%.c
$(CC) -c `$(PCONF1)` $<

which is not compiling the $(SUBDIR)/%.c files at all, with make giving error:

$ make
gcc `pkg-config --cflags --libs gtk+-2.0` help.c table.c -o ptbl
/tmp/ccOKcWuf.o: In function `main':
table.c.text+0xa9a): undefined reference to `callback_A'
table.c.text+0xb3a): undefined reference to `callback_B'
.....
and so on

but if I try to compile directly,
gcc -g table.c help.c files/prop_*.c `pkg-config --cflags --libs ^Ck+-2.0` -o ptbl
its working fine.
Can anybody please show me the error?

 

[Rudra Banerjee]

gcc -g table.c help.c files/prop_*.c `pkg-config --cflags --libs gtk+-2.0` -o ptbl

 

[Casey Carter]

objects := $(wildcard $(SUBDIR)/*.o)

$(wildcard $(SUBDIR)/*.o) will be empty unless the object files are
compiled already. Try:

sources := $(wildcard $(SUBDIR)/*.c)
objects := $(sources:.c=.o)

 

[Rudra Banerjee]

sources := $(wildcard $(SUBDIR)/*.c)

objects := $(sources:.c=.o)

Thanks,
Its working.
Though it was creating the .o files of SUBDIR source in maindir.
so I did:
exe=ptbl
CC=gcc
CFLAGS =-O3
SUBDIR=files
PCONF1=pkg-config --cflags --libs gtk+-2.0
sources := $(wildcard $(SUBDIR)/*.c)
objects := $(sources:.c=.o)
$(exe): $(objects) help.c table.c callbk_list.h cwlst.h
$(CC) `$(PCONF1)` $(objects) help.c table.c -o $(exe)

$(SUBDIR)/%.o: $(SUBDIR)/%.c
$(CC) -c `$(PCONF1)` $<
mv $(*F).o $(SUBDIR)/$(*D)

and moved the files back to SUBDIR.
is there any way to create the .o of SUBDIR/*.c in SUBDIR only?

 

[Jorgen Grahn]

%.o: %.c
$(CC) ...

Which is the builtin rule in Gnu make, so you can omit it and not
write anything at all! If you need something special per subdirectory
you can e.g. do this without overriding the default rule:

test/%.o: CPPFLAGS+=-I.

there is one more thing missing here - the dependencies on header files.

you might just prefer to use ready-to-go solution. i've once wrote
generic makefile for compiling all files in the current directory and
subdirectories:
https://github.com/el-bart/build_process/tree/master/small_prj_build_process
it also tracks dependencies, allows to build automated and manual tests,
debug, release. all builds are done in a separate directory.

Well, yeah, as long as he can still understand roughly what's going
on. I've seen enough people treating the Makefiles as magic which they
don't have to understand or care about.

/Jorgen

 

[Casey Carter]

Thanks,
Its working.
Though it was creating the .o files of SUBDIR source in maindir.
so I did:
exe=ptbl
CC=gcc
CFLAGS =-O3
SUBDIR=files
PCONF1=pkg-config --cflags --libs gtk+-2.0
sources := $(wildcard $(SUBDIR)/*.c)
objects := $(sources:.c=.o)
$(exe): $(objects) help.c table.c callbk_list.h cwlst.h
$(CC) `$(PCONF1)` $(objects) help.c table.c -o $(exe)

$(SUBDIR)/%.o: $(SUBDIR)/%.c
$(CC) -c `$(PCONF1)` $<
mv $(*F).o $(SUBDIR)/$(*D)

and moved the files back to SUBDIR.
is there any way to create the .o of SUBDIR/*.c in SUBDIR only?

Add your `$(PCONF1)` into CFLAGS, and get rid of the compiling rule.
make's default rules should build everything properly:

exe = ptbl
PCONF1 := $(shell pkg-config --cflags --libs gtk+-2.0)
CC = gcc
CFLAGS = -O3 $(PCONF1)
SUBDIR = files
sources := $(wildcard $(SUBDIR)/*.c)
objects := $(sources:.c=.o)

$(exe): $(objects) help.c table.c callbk_list.h cwlst.h