manchester encoder

Discussion in 'VHDL' started by Ronny Hengst, Aug 7, 2003.

  1. Ronny Hengst

    Ronny Hengst Guest

    Hello everybody

    From a student a got the code below. It is a manchster encoder realized as
    moore - finite state machine + testbench. The encoder doesn't detect the
    rising edge of the input and detects a logical one as zero. Can anybody
    help me? Please!

    LIBRARY ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.std_logic_arith.all ;

    ENTITY manchesterE IS
    PORT ( clk : in std_logic;
    reset : in std_logic;
    NRZ : in std_logic;
    flag: out std_logic;
    z : out std_logic
    );
    END manchesterE ;

    ARCHITECTURE fsm_man OF manchesterE IS
    -- Architecture Declarations
    TYPE STATE_TYPE IS ( s0,s1,s2,s3 );

    -- Declare current and next state signals
    SIGNAL current_state : STATE_TYPE ;
    SIGNAL next_state : STATE_TYPE ;

    BEGIN
    --------------------------------------------------------------------------
    --
    clocked : PROCESS(
    clk,
    reset
    )
    -------------------------------------------------------------------------
    ---
    BEGIN
    IF (reset = '0') THEN
    current_state <= s0;
    -- Reset Values
    ELSIF (clk'EVENT AND clk = '1') THEN
    current_state <= next_state;
    -- Default Assignment To Internals

    END IF;

    END PROCESS clocked;

    -------------------------------------------------------------------------
    ---
    nextstate : PROCESS (
    current_state,
    NRZ
    )
    -------------------------------------------------------------------------
    ---
    BEGIN
    CASE current_state IS
    WHEN s0 =>
    next_state <= s0;
    IF (NRZ = '0') THEN
    next_state <= s1;
    END IF;
    IF (NRZ = '1') THEN
    next_state <= s3;
    END IF;
    WHEN s1 =>
    IF (NRZ = '0') THEN
    next_state <= s2;
    ELSE
    next_state <= s1;
    END IF;
    WHEN s2 =>
    next_state <= s2;
    IF (NRZ = '0') THEN
    next_state <= s1;
    END IF;
    IF (NRZ = '1') THEN
    next_state <= s3;
    END IF;
    WHEN s3 =>
    IF (NRZ = '1') THEN
    next_state <= s0;
    ELSE
    next_state <= s3;
    END IF;
    WHEN OTHERS =>
    next_state <= s0;
    END CASE;

    END PROCESS nextstate;

    -------------------------------------------------------------------------
    ---
    output : PROCESS (
    current_state
    )
    -------------------------------------------------------------------------
    ---
    BEGIN
    -- Default Assignment
    z <= '0';
    -- Default Assignment To Internals

    -- Combined Actions
    CASE current_state IS
    WHEN s0 =>
    z <= '1' ;
    flag <= '0';
    WHEN s1 =>
    z <= '0' ;
    flag <= '1';
    WHEN s2 =>
    z <= '1';
    flag <= '0';
    WHEN s3 =>
    z <= '1' ;
    flag <= '1';
    WHEN OTHERS =>
    NULL;
    END CASE;

    END PROCESS output;

    -- Concurrent Statements

    END fsm_man;
    ---------------------------------------------------Testbench
    library IEEE;
    use ieee.numeric_std.all;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ENTITY tb_manchester IS
    END tb_manchester;

    ARCHITECTURE verhalten OF tb_manchester IS

    COMPONENT manchesterE
    PORT( clk : in std_logic;
    reset : in std_logic;
    NRZ : in std_logic;
    flag: out std_logic;
    z : out std_logic
    );
    END COMPONENT;

    COMPONENT manchesterD
    PORT( clk : IN std_logic;
    reset : IN std_logic;
    flag : IN std_logic;
    z : IN std_logic;
    NRZ : OUT std_logic
    );
    END COMPONENT;


    SIGNAL streambit: std_logic;
    SIGNAL tb_in: std_logic_vector(11 DOWNTO 0);

    SIGNAL tb_clk, tb_reset : std_logic;
    SIGNAL tb_out : std_logic;
    SIGNAL tb_Z : std_logic;
    SIGNAL count : std_logic_vector (7 downto 0);
    SIGNAL tb_flag : std_logic;

    BEGIN

    uut_E : manchesterE
    PORT MAP(
    clk => tb_clk,
    reset => tb_reset,
    NRZ => tb_out,
    flag => tb_flag,
    z => tb_Z
    );

    uut_D : manchesterD
    PORT MAP(
    clk => tb_clk,
    reset => tb_reset,
    --NRZ => tb_out,
    flag => tb_flag,
    z => tb_Z
    );

    Shift_Out : process (tb_clk)

    begin

    if tb_reset = '0' then

    tb_in <= "001110101101";
    streambit <= '0';
    tb_out <= '0';
    count <= (others => '0');

    else

    if tb_clk'event and tb_clk = '1' then

    streambit <= tb_in(11) xor tb_in(7);
    tb_in( 11 downto 0) <= tb_in( 10 downto 0) & streambit;

    if count(0) = '0' then
    tb_out <= tb_in(11);
    END IF; count <= count + '1';
    end if;

    end if;
    end process Shift_Out;
    -- ------------------------------------------
    -- Clk Generation
    Clk_Gen : process
    begin

    -- 25 MHZ >> LOW: 20 ns, HIGH: 20 ns
    tb_clk <= '0';
    wait for 10 ns;

    tb_clk <= '1';
    wait for 10 ns;

    end process Clk_Gen;
    -- ------------------------------------------
    -- Reset Generation

    Reset_Gen : process
    begin

    tb_reset <= '1';
    wait for 5 ns;

    tb_reset <= '0';
    wait for 13 ns;

    tb_reset <= '1';
    wait;
    end process reset_Gen;
    end verhalten;
     
    Ronny Hengst, Aug 7, 2003
    #1
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  2. Ronny Hengst

    Ronny Hengst Guest

    Ronny Hengst, Aug 8, 2003
    #2
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  3. "Ronny Hengst" <> wrote in message
    news:...
    > The state machine seems to be from
    >
    > http://www.fpga.com.cn/application/safe_sm_12157.pdf
    >
    > and I think it is correct.


    It is a correct description of the wrong state machine.
    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Aug 8, 2003
    #3
  4. Ronny Hengst

    Ronny Hengst Guest

    > It is a correct description of the wrong state machine.
    > --
    >
    > Jonathan Bromley, Consultant


    And the write one is......?
     
    Ronny Hengst, Aug 8, 2003
    #4
  5. "Ronny Hengst" <> wrote in message
    news:bh021v$svjpn$-berlin.de...

    > > It is a correct description of the wrong state machine.


    > And the write one is......?


    Any one of the infinite set of state machines that
    (a) does not suffer the same error that appears to
    exist in the Mentor appnote you quoted;
    (b) meets your specification, which so far you have
    not vouchsafed to us.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Aug 8, 2003
    #5
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