mandatory output binding?

Discussion in 'VHDL' started by valentin tihomirov, Jul 2, 2005.

  1. the outputs of a component being instantiated can be left 'open' if the
    vector range is defined

    entity E is
    port map (
    O: out std_logic_vector(1 to 10);


    However, the simulatior enforces me to bind the O signal for the component
    declared as:

    entity E is
    port map (
    I: in std_logic_vector;
    O: out std_logic_vector; -- assumed to be the I'range
    ...

    e: entity E is (O => open, ) -- error here

    Just a bug in my simulator?
     
    valentin tihomirov, Jul 2, 2005
    #1
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  2. On Sat, 2 Jul 2005 19:52:59 +0300, "valentin tihomirov"
    <> wrote:


    >However, the simulatior enforces me to bind the O signal for the component
    >declared as:
    >
    > entity E is
    > port map (
    > I: in std_logic_vector;
    > O: out std_logic_vector; -- assumed to be the I'range
    > ...
    >
    > e: entity E is (O => open, ) -- error here
    >
    >Just a bug in my simulator?


    No, I don't think so. If you don't bind the unconstrained
    array then it remains unconstrained within the entity/architecture,
    and that makes no sense. For example, what would happen if you
    tried to make use of "O'length" within the architecture?

    By the way Valentin, I think that I and many others here would
    appreciate an occasional acknowledgement of whether our
    responses to you are helpful or not. Many of your questions
    are quite intriguing and I'm sure people will continue to
    answer them, but our answers seem to go into a black hole :-(
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Jul 4, 2005
    #2
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