Manipulating with the T1, T0 and TX in a SAIF file.

Discussion in 'VHDL' started by Kelvin Tsai @ Singapore, Sep 9, 2003.

  1. Hi, all:

    In my gate-level simulation without SDF, specifically for power
    analysis, Verilog-XL uses the built-in delay in each gate, which
    means 1ns...but the levels of some paths are bigger than my clock
    rate...

    In my simulation I doubled the clock period...but the toggle rate will
    half...

    If I write a script to divide all the "DURATION", TC0, TC1, and TX by
    half, will it work correctly?

    Thanks.

    By the way does the "-scale " in the read_saif have anything to do
    with the `timescale in my simulation? People told me he used -scale 1
    and -scale 10 but got same power, so what is this -scale used for?

    Best Regards,
    Kelvin.
     
    Kelvin Tsai @ Singapore, Sep 9, 2003
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. New to Power Analysis

    Any idea about generating SAIF files ?

    New to Power Analysis, Oct 20, 2004, in forum: VHDL
    Replies:
    3
    Views:
    966
    Jon Beniston
    Oct 22, 2004
  2. abhishek

    VHDL and SAIF

    abhishek, Jan 7, 2005, in forum: VHDL
    Replies:
    1
    Views:
    833
    Mohammed khader
    Jan 7, 2005
  3. C-man
    Replies:
    1
    Views:
    6,272
    Andrew Thompson
    Nov 3, 2003
  4. Sean Davis
    Replies:
    2
    Views:
    331
    Lawrence D'Oliveiro
    Aug 26, 2007
  5. soren625
    Replies:
    20
    Views:
    278
    Ian Wilson
    Dec 28, 2005
Loading...

Share This Page