map error about input signals of state machine that will be trimmed

Discussion in 'VHDL' started by Steven Kauffmann, Dec 18, 2007.

  1. Hello all,

    The following process causes the error about the trimmed signals.

    process(output_port_component)
    begin
    ready <= not(ready);
    end process;

    The process has to invert the ready signal when the data on the output
    port of the component changes. I use this ready signal in a state
    machine. In this state machine I check if this ready signal is
    changed. During the mapping of this VHDL code I get the error that
    some input signals of this state machine will be trimmed. If I put in
    comment the process above and also the check on the ready signal in
    the state machine than I get no errors.

    I can solve the errors by editing the map properties and unset the
    option "trim unconnected signals". But than my design is not working
    like I would expect. I connected the ready signal to a led available
    on the board but this led is not changing. I also connect it to a
    scope to see if it was not changing to frequent but that is also not
    the case. I'm for 100% sure that the output port of the component is
    changing but why not the ready signal?

    Thanks in advance

    Steven
     
    Steven Kauffmann, Dec 18, 2007
    #1
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  2. Steven Kauffmann

    JK Guest

    Re: map error about input signals of state machine that will betrimmed

    On Dec 18, 7:48 pm, Steven Kauffmann <>
    wrote:
    >
    > The process has to invert the ready signal when the data on the output
    > port of the component changes. I use this ready signal in a state
    > machine. In this state machine I check if this ready signal is
    > changed.


    process(state_machine_clock)
    begin
    if rising_edge(state_machine_clock) then
    if (output_port_component'event) then
    ready <= (not ready);
    end if;
    end if;
    end process;

    Regards,
    JK
     
    JK, Dec 18, 2007
    #2
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  3. Re: map error about input signals of state machine that will betrimmed

    On Dec 18, 7:19 pm, JK <> wrote:
    > On Dec 18, 7:48 pm, Steven Kauffmann <>
    > wrote:
    >
    >
    >
    > > The process has to invert the ready signal when the data on the output
    > > port of the component changes. I use this ready signal in a state
    > > machine. In this state machine I check if this ready signal is
    > > changed.

    >
    > process(state_machine_clock)
    > begin
    > if rising_edge(state_machine_clock) then
    > if (output_port_component'event) then
    > ready <= (not ready);
    > end if;
    > end if;
    > end process;
    >


    The output_port_component is a std_logic_vector and not a std_logic
    signal so the event is not usable or am I wrong? When using an event
    you also have to specify the level of the signal eg.
    (output_port_component'event and output_port_component = '1') the
    event alone is not a correct syntax according to the XST synthesizer.

    If I use this code
    process(state_machine_clock)
    begin
    if rising_edge(state_machine_clock) then
    if (output_port_component(0)'event and output_port_component(0) =
    '1') then
    ready <= (not ready);
    end if;
    end if;
    end process;

    But this gives the following error:
    Sequential logic for node <ready> appears to be controlled by multiple
    clocks.

    And this error is because I use 2 events in 1 process I think.

    Regards
    Steven
     
    Steven Kauffmann, Dec 20, 2007
    #3
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