mapping bidirectional busses

[dev ranjan das]

I am a new to VHDL coding.I have instantiated two components having a
bidirectional bus each.Now I am having a problem mapping these bus.I
use Max Plus II and I am targettimg on Altera Flex 10k50E..can anybody
guide me how to map bidirectional busses..

suppose component1
dat1: inout std_logic_vector(31 downto 0);
component2
dat2:inout std_logic_vector(31 downto 0);

dat1 and dat2 are to be connected or mapped..

U1:component1 port map( dat1=>x1)
U2:component2 port map( dat2=>x1)

this mapping doesnt work and error message says "x1 has multiple
sources"

please guide..
dev

 

[Ralf Hildebrandt]

dev ranjan das wrote:

suppose component1
dat1: inout std_logic_vector(31 downto 0);
component2
dat2:inout std_logic_vector(31 downto 0);

dat1 and dat2 are to be connected or mapped..

U1:component1 port map( dat1=>x1)
U2:component2 port map( dat2=>x1)

this mapping doesnt work and error message says "x1 has multiple
sources"

x1 has to be a std_logic_vector, too. (resolved data type)

Take care, that always only one driver is driving the bus. All others
should be 'Z', when not active.


Ralf

 

[Renaud Pacalet]

dev ranjan das a écrit :

I am a new to VHDL coding.I have instantiated two components having a
bidirectional bus each.Now I am having a problem mapping these bus.I
use Max Plus II and I am targettimg on Altera Flex 10k50E..can anybody
guide me how to map bidirectional busses..

suppose component1
dat1: inout std_logic_vector(31 downto 0);
component2
dat2:inout std_logic_vector(31 downto 0);

dat1 and dat2 are to be connected or mapped..

U1:component1 port map( dat1=>x1)
U2:component2 port map( dat2=>x1)

this mapping doesnt work and error message says "x1 has multiple
sources"

please guide..

First idea:
-----------
How did you declare x1? It must be of type std_logic_vector and not
std_ulogic_vector because it has several sources and needs a resolution function
in order to compute its actual value from the different values of the different
sources. In std_ulogic_vector the 'u' stands for unresolved. std_logic_vector is
a subtype of std_ulogic_vector resolved by a resolution function (see package
ieee.std_logic_1164).

Second idea:
------------
Max Plus II beeing a synthesizer it translates your description into hardware.
If the hardware target you selected has no 3-states buffers it may be impossible
for Max Plus II to synthesize your description. As far as I remember Flex10k
have inout pads but I don't remember anything about internal 3-states buffers.
Any Altera guru there?

Regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
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