matched delays in Xilinx ISE?

Discussion in 'VHDL' started by David Tweed, May 26, 2005.

  1. David Tweed

    David Tweed Guest

    I have a Spartan 3 with two Tigersharc link ports connected to it.
    I would like to use the FPGA to connect the two ports directly to
    each other, with no registers or other logic in the path. The problem
    I have is that because of how the pins are assigned, the clock path
    is very short (0.818 ns) and the data path is very long (3.619 ns)
    inside the FPGA. This skew (2.8 ns) is more than the DSP can tolerate.
    Is there a way to specify a timing constraint within a group of two
    or more unclocked signals so that the delays are matched to within
    some tolerance even if I don't care what the absolute delay is?

    I'm hoping to at least be able to route the clock through a similar
    number of "long lines" and "switch boxes" as required for the data
    path, even though this wouldn't be the most direct path.

    I've even tried to figure out how to do manual routing in the chip
    editor, but the documentation is too sketchy and I can't get it to
    work. Has anyone done manual routing in ISE?

    I notice that SP2 for ISE 7.1i is now out. Has anyone tried it yet?
    Is it time for me to upgrade from ISE 6.3i SP3?

    -- Dave Tweed
     
    David Tweed, May 26, 2005
    #1
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