M
Moises
Hello,
My name is Moises Paniagua and I am designing a communication interface
in VHDL. I would be grateful if any of you could help me.
My problem is that I have a matrix and I would like to pick up its rows
and register them in a vector of vectors. Find attached the types used
and the part of code, which I am designing.
Many thanks for advance,
Moises Paniagua
type data_out is array(0 to MAT_LENGTH-1,0 to MAT_WIDTH-1) of
std_logic_vector(MAX_BIT-1 downto 0);
type sum_c is array(0 to MAT_LENGTH-1) of
std_logic_vector(MAX_BIT-1 downto 0);
type conv is array(0 to MAT_WIDTH-1) of sum_c;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.librairie.all;
entity convert is
Generic(
length : natural := MAT_LENGTH;
width : natural := MAT_WIDTH);
Port ( input : in data_out;
output : out conv);
end convert;
architecture behaviour of convert is
signal aux : conva;
begin
L1: for i in 0 to width-1 generate
L2: for j in 0 to length-1 generate
aux(i) of sum_c(j) <= input(j, i);
end generate;
end generate;
output <= aux;
end behaviour;
My name is Moises Paniagua and I am designing a communication interface
in VHDL. I would be grateful if any of you could help me.
My problem is that I have a matrix and I would like to pick up its rows
and register them in a vector of vectors. Find attached the types used
and the part of code, which I am designing.
Many thanks for advance,
Moises Paniagua
type data_out is array(0 to MAT_LENGTH-1,0 to MAT_WIDTH-1) of
std_logic_vector(MAX_BIT-1 downto 0);
type sum_c is array(0 to MAT_LENGTH-1) of
std_logic_vector(MAX_BIT-1 downto 0);
type conv is array(0 to MAT_WIDTH-1) of sum_c;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.librairie.all;
entity convert is
Generic(
length : natural := MAT_LENGTH;
width : natural := MAT_WIDTH);
Port ( input : in data_out;
output : out conv);
end convert;
architecture behaviour of convert is
signal aux : conva;
begin
L1: for i in 0 to width-1 generate
L2: for j in 0 to length-1 generate
aux(i) of sum_c(j) <= input(j, i);
end generate;
end generate;
output <= aux;
end behaviour;