Max clock rates in standard cell?

Discussion in 'VHDL' started by Tim Neeson, Jun 23, 2006.

  1. Tim Neeson

    Tim Neeson Guest

    [off-topic, and sorry about the cross-post: there seem to be no NGs
    which are relevant...]

    I'm trying to get some idea of usable maximum frequencies at 90 -
    130nm in standard cell. I have one ballpark estimate of about 300MHz
    for 130nm, and 400MHz for 110nm, with ~4/5 levels of logic.

    However, if I just add up raw gate delays, it seems that it should be
    possible to go at about twice this speed. Does anyone have any better
    estimates, or examples of faster chips? Is 800MHz+ achievable on 90nm,
    or 600MHz on 110nm?

    If not, any idea what the limiting factors are, and why clock rate
    doesn't scale with logic levels? Is this down to silicon timing
    uncertainties?

    TIA -

    Tim
     
    Tim Neeson, Jun 23, 2006
    #1
    1. Advertising

  2. Tim Neeson

    mk Guest

    On Fri, 23 Jun 2006 09:59:49 +0100, Tim Neeson <>
    wrote:

    >[off-topic, and sorry about the cross-post: there seem to be no NGs
    >which are relevant...]
    >
    >I'm trying to get some idea of usable maximum frequencies at 90 -
    >130nm in standard cell. I have one ballpark estimate of about 300MHz
    >for 130nm, and 400MHz for 110nm, with ~4/5 levels of logic.
    >
    >However, if I just add up raw gate delays, it seems that it should be
    >possible to go at about twice this speed. Does anyone have any better
    >estimates, or examples of faster chips? Is 800MHz+ achievable on 90nm,
    >or 600MHz on 110nm?
    >
    >If not, any idea what the limiting factors are, and why clock rate
    >doesn't scale with logic levels? Is this down to silicon timing
    >uncertainties?


    I am assuming you're considering the setup times of the flops. Other
    considerations are clock tree skew, clock jitter and power.
    Effectively your minimum period is clk->Q+comb delay + clock skew +
    jitter + setup. Of course you have to keep leakage and dynamic power
    at a reasonable rate.
    That said, if you limit your logic levels to 4 and have a decent
    library, it is possible to achieve 500 MHz with 130nm and 800 MHz with
    90nm but that requires quite a bit of effort (tight clock tree, manual
    timing ecos etc.)
     
    mk, Jun 23, 2006
    #2
    1. Advertising

  3. Tim Neeson

    Tim Neeson Guest

    On Fri, 23 Jun 2006 16:15:16 GMT, mk<kal*@dspia.*comdelete> wrote:
    <snipped>

    Thanks - useful info.

    Tim
     
    Tim Neeson, Jun 27, 2006
    #3
  4. Tim Neeson

    Guest

    > I have one ballpark estimate of about 300MHz for 130nm

    Easy.

    > >However, if I just add up raw gate delays, it seems that it should be
    > >possible to go at about twice this speed.


    Don't forget routing delay.

    > Does anyone have any better estimates, or examples of faster chips?


    ARM claim 333 - 550Mhz for ARM1136J-S in .13.

    > Is 800MHz+ achievable on 90nm,


    Yep.

    Cheers,
    Jon
     
    , Jul 5, 2006
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Valentin Tihomirov

    Are clock and divided clock synchronous?

    Valentin Tihomirov, Oct 23, 2003, in forum: VHDL
    Replies:
    11
    Views:
    3,341
    louis lin
    Oct 28, 2003
  2. Abs
    Replies:
    0
    Views:
    523
  3. Abs
    Replies:
    0
    Views:
    410
  4. Abs
    Replies:
    0
    Views:
    437
  5. Abs
    Replies:
    0
    Views:
    491
Loading...

Share This Page