Memory controler

Discussion in 'VHDL' started by 082080112, Jan 11, 2010.

  1. 082080112

    082080112

    Joined:
    Jan 11, 2010
    Messages:
    1
    Likes Received:
    0
    I am designing DDR2 MEMORY CONTROLLER using VHDL with Vertex 4 of XILINX , but I am not getting how can I get two differential clock output.

    From JEDEC DDR2 standard clock CK and CK# are differential clock inputs to sdram from memory controller output. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).

    Have anybody Idea how to write VHDL code of above problem ?
     
    082080112, Jan 11, 2010
    #1
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Mahesh Prasad
    Replies:
    1
    Views:
    866
    Tom Wells
    Feb 22, 2004
  2. Cy Huckaba
    Replies:
    1
    Views:
    1,324
    Xie Xiao
    Jun 26, 2003
  3. Olof
    Replies:
    3
    Views:
    446
    Alvin Bruney [MVP]
    Mar 5, 2004
  4. Julián Sanz García

    RAM Memory or virual memory

    Julián Sanz García, Nov 12, 2004, in forum: ASP .Net
    Replies:
    4
    Views:
    1,022
    Julián Sanz García
    Nov 12, 2004
  5. Seb
    Replies:
    2
    Views:
    741
  6. humbleaptience
    Replies:
    0
    Views:
    5,723
    humbleaptience
    Feb 22, 2006
  7. Seb
    Replies:
    3
    Views:
    258
  8. Olivier Matrot
    Replies:
    2
    Views:
    302
    Olivier Matrot
    Mar 15, 2007
Loading...