I am designing DDR2 MEMORY CONTROLLER using VHDL with Vertex 4 of XILINX , but I am not getting how can I get two differential clock output.
From JEDEC DDR2 standard clock CK and CK# are differential clock inputs to sdram from memory controller output. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).
Have anybody Idea how to write VHDL code of above problem ?
From JEDEC DDR2 standard clock CK and CK# are differential clock inputs to sdram from memory controller output. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).
Have anybody Idea how to write VHDL code of above problem ?