Memory synthesis using VHDL - Errors

Discussion in 'VHDL' started by strykaar, Oct 23, 2006.

  1. strykaar

    strykaar

    Joined:
    Aug 28, 2006
    Messages:
    3
    Hi friends I am trying to implement memory using VHDL and below is the code for that. I have a limitation that my address bus has to be 19 bits wide and data bus 8 bits, I am getting the following errors in the order mentioned:

    1. parse error, unexpected LIBRARY, expecting error or IDENTIFIER
    2. Library IEEE is not declared.


    these point out at the very beginning on the code :

    USE library IEEE;
    USE IEEE.STD_LOGIC_1164.all;

    package RAM_package is
    subtype addr is std_logic_vector (18 downto 0);
    type MEM is array (524287 downto 0) of addr;
    end RAM_package;

    USE WORK.RAM_package.ALL;
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity ram_1 is
    port (A : in std_logic_vector(18 downto 0) :="0000000000000000000";
    CEB, WEB, OEB : out STD_LOGIC;
    data : inout std_logic_vector(7 downto 0));
    end ram_1;

    architecture Behavioral of ram_1 is

    signal i_bus : std_logic_vector(7 downto 0) := "00000000"; -- RAM internal data latch
    signal mem : MEM; -- RAM data

    begin
    process begin

    variable i: integer;

    for i in 0 to 128 loop

    wait until CEB = '0';

    if WEB = '1' then --- read op

    i_bus <= mem(A);

    elsif WEB = '0' then -- write op
    mem(A) <= data;
    i_bus <= data;

    else i_bus <= ( others => 'X');

    end if ;
    A<=A+1;
    end loop;
    end process ;

    process (OEB, i_bus) begin -- control output drivers:
    case (OEB) is
    when '0' => data <= i_bus;
    when '1' => data <= ( others => 'Z');
    when others => data <= ( others => 'X');
    end case ;
    end process ;

    end Behavioral;
     
    strykaar, Oct 23, 2006
    #1
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