Microprocessor memory

Discussion in 'VHDL' started by Stefan Duenser, Jan 6, 2005.

  1. Hello

    I have implemented a very easy memory with a few registers, where i can
    store and also read values for and from my ALU:

    I have got 2 questions:

    1) The conv_integer procedure does not work here, I always get the
    errormessage: no feasable subprogram entry for conv_integer
    2) Finally this memory should be synthizeable for a Xilinx ML300 board. What
    do I have to change that this will be alright?
    Is there a documention available? I wasnt able to find one online

    Thanks for your help and time!

    Cheers

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity memory is
    generic (width : integer := 32);
    port (clk : in std_ulogic;
    rst : in std_ulogic;
    inp : in std_ulogic_vector((2*width-1) downto 0);
    addr: in std_ulogic_vector(3 downto 0);
    wr : in std_ulogic;
    rd : in std_ulogic;
    outp: out std_ulogic_vector((2*width-1) downto 0)
    );
    end memory;

    architecture rtl of memory is

    type reg_type is array (0 to 3) of std_ulogic_vector((2*width-1) downto
    0);
    signal reg_file : reg_type;

    begin

    write : process(clk,rst,inp,addr,wr)
    variable x_int : integer;
    begin
    if rst = '1' then
    reg_file(0) <= (others => '0');
    else
    if clk'event and clk = '1' then
    if wr = '1' then
    reg_file(conv_integer(addr)) <= inp;
    end if;
    end if;
    end if;
    end process;

    read : process(clk,rst,addr,rd)
    begin
    if rst = '1' then
    outp <= (others => '0');
    else
    if clk'event and clk = '1' then
    if rd = '1' then
    outp <= reg_file(conv_integer(addr));
    end if;
    end if;
    end if;
    end process;

    end rtl;
    Stefan Duenser, Jan 6, 2005
    #1
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  2. > 1) The conv_integer procedure does not work here, I always get the
    > errormessage: no feasable subprogram entry for conv_integer. Any ideas
    > whats wrong here?


    I really dont understand why this is not working, because this functions are
    declared in the ieee.std_logic_arith.all header...

    FUNCTION to_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN
    INTEGER;
    FUNCTION to_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN
    INTEGER;
    FUNCTION to_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN
    NATURAL;
    FUNCTION to_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL;
    FUNCTION to_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;

    FUNCTION conv_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 )
    RETURN INTEGER;
    FUNCTION conv_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 )
    RETURN INTEGER;
    FUNCTION conv_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN
    NATURAL;
    FUNCTION conv_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN
    NATURAL;
    FUNCTION conv_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER

    any useful tips?
    Stefan Duenser, Jan 6, 2005
    #2
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  3. "Stefan Duenser" <> schreef in bericht
    news:...
    >> 1) The conv_integer procedure does not work here, I always get the
    >> errormessage: no feasable subprogram entry for conv_integer. Any ideas
    >> whats wrong here?

    >
    > I really dont understand why this is not working, because this functions
    > are declared in the ieee.std_logic_arith.all header...
    >
    > FUNCTION to_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 )
    > RETURN INTEGER;
    > FUNCTION to_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN
    > INTEGER;
    > FUNCTION to_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN
    > NATURAL;
    > FUNCTION to_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN
    > NATURAL;
    > FUNCTION to_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;
    >
    > FUNCTION conv_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 )
    > RETURN INTEGER;
    > FUNCTION conv_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 )
    > RETURN INTEGER;
    > FUNCTION conv_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN
    > NATURAL;
    > FUNCTION conv_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN
    > NATURAL;
    > FUNCTION conv_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER
    >
    > any useful tips?
    >


    If I have a look at the functions that are in your package std_logic_arith I
    think that you are not using the Synopsys package std_logic_arith.
    I can imagine you created your own package compiled it into library work and
    use unintentionally the package that is in de library IEEE.

    For the synopsys package you have to write: (notice the type conversion)
    reg_file(conv_integer(std_logic_vector(addr))) <= inp;

    Egbert Molenkamp
    Egbert Molenkamp, Jan 6, 2005
    #3
  4. Try this.
    -- Mike Treseler
    ------------------------------------------------------
    -- Thu Jan 6 10:21:41 2005 register memory example
    -- by Stefan Duenser cleaned up by Mike Treseler
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity memory is
    generic (width : integer := 32);
    port (clk : in std_ulogic;
    rst : in std_ulogic;
    inp : in std_ulogic_vector((2*width-1) downto 0);
    addr : in std_ulogic_vector(3 downto 0);
    wr : in std_ulogic;
    rd : in std_ulogic;
    outp : out std_ulogic_vector((2*width-1) downto 0)
    );
    end memory;

    architecture rtl of memory is
    type reg_type is array (0 to 3)
    of std_ulogic_vector((2*width-1) downto 0);
    signal reg_file : reg_type;
    begin
    one : process(clk, rst)
    variable x_int : integer;
    begin
    if rst = '1' then
    x_int := 0;
    else
    if clk'event and clk = '1' then
    x_int := to_integer(unsigned(addr));
    if wr = '1' then
    reg_file(x_int) <= inp;
    elsif rd = '1' then
    outp <= reg_file(x_int);
    end if;
    end if;
    end if;
    end process one;
    end rtl;
    Mike Treseler, Jan 6, 2005
    #4
  5. "Mike Treseler" <> wrote in message
    news:...
    > Try this.


    Thanks a lot Mike, it worked!! Also thanks for your hint Egbert!

    Bye
    Stefan Duenser, Jan 6, 2005
    #5
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