mixed hdl synthesis

Discussion in 'VHDL' started by bxbxb3, Mar 23, 2005.

  1. bxbxb3

    bxbxb3 Guest

    Hi,
    Can anyone please tell me how to carry out mixed hdl synthesis in LEOSPEC,
    my TOP LEVEL is in VHDL
    one LOwer block in VERILOG and other in VHDL
    the tool shows SYNTAX errors. What i got from there is that if u r
    synthesizing VERILOG file then it will not take VHDL syntaxes and vice-
    versa. How to carry out that
    one more problem related to XILINX COREGEN ,
    when i instantiate it from coregen and save the top level as either .v or
    vhd it sometimes carries out TRANSLATION but sometimes it does not works

    or i need to insert corresponding .XCO file of that instantiated coregen
    everytime
    please tell me the correct way of doing this.
    bxbxb3, Mar 23, 2005
    #1
    1. Advertising

  2. bxbxb3

    Neo Guest

    Actually you should have no problem but have you checked whether you
    have the license for mixed language design.
    Neo, Mar 24, 2005
    #2
    1. Advertising

  3. bxbxb3

    bxbxb3 Guest

    Thanks for the advice, It works in advanced mode of LeoSpec.
    bxbxb3, Mar 29, 2005
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    4
    Views:
    2,096
    Ralf Hildebrandt
    Sep 8, 2003
  2. Lesalesa

    Mixed HDL Simulation-Query

    Lesalesa, Sep 18, 2006, in forum: VHDL
    Replies:
    0
    Views:
    530
    Lesalesa
    Sep 18, 2006
  3. devices

    On HDL Synthesis

    devices, Jun 25, 2007, in forum: VHDL
    Replies:
    12
    Views:
    868
    devices
    Jul 4, 2007
  4. Replies:
    1
    Views:
    586
    Ralf Hildebrandt
    Nov 7, 2007
  5. digital pig

    HDL - simulation vs synthesis

    digital pig, May 28, 2008, in forum: VHDL
    Replies:
    1
    Views:
    544
    digital pig
    May 29, 2008
Loading...

Share This Page