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Hi,
Can anyone please tell me how to carry out mixed hdl synthesis in LEOSPEC,
my TOP LEVEL is in VHDL
one LOwer block in VERILOG and other in VHDL
the tool shows SYNTAX errors. What i got from there is that if u r
synthesizing VERILOG file then it will not take VHDL syntaxes and vice-
versa. How to carry out that
one more problem related to XILINX COREGEN ,
when i instantiate it from coregen and save the top level as either .v or
vhd it sometimes carries out TRANSLATION but sometimes it does not works
or i need to insert corresponding .XCO file of that instantiated coregen
everytime
please tell me the correct way of doing this.
Can anyone please tell me how to carry out mixed hdl synthesis in LEOSPEC,
my TOP LEVEL is in VHDL
one LOwer block in VERILOG and other in VHDL
the tool shows SYNTAX errors. What i got from there is that if u r
synthesizing VERILOG file then it will not take VHDL syntaxes and vice-
versa. How to carry out that
one more problem related to XILINX COREGEN ,
when i instantiate it from coregen and save the top level as either .v or
vhd it sometimes carries out TRANSLATION but sometimes it does not works
or i need to insert corresponding .XCO file of that instantiated coregen
everytime
please tell me the correct way of doing this.