mixed Verilog/VHDL design

[botao]

Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee

 

[Kai Harrekilde-Petersen]

Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

AFAIK, you loose. Verilog has no understanding of Libraries, so it's a
plain no-go.


--Kai

 

[botao]

anybody hate verilog

 

[Jonathan Bromley]

AFAIK, you loose. Verilog has no understanding of Libraries, so it's a
plain no-go.

Not entirely true. Find out about the `uselib directive (not
all tools support it). Then there's the Verilog-2001 library and
configuration mechanism; again, tool support is variable, and
some aspects of the standard are left for tool vendors to
define anyway.

The basic problem is that a library in Verilog, whether implemented
through `uselib or V2k1 library/configuration, is a collection of
source files, whereas a VHDL library is a collection of compiled
design units. Mixed-language tools have the unenviable task
of making these two things interoperate sensibly.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Just an Illusion]

In fact you can mix the both components, but perhaps no so simple taht
expected.

You can instanciate the both component into the same top level file, if
the top is a vhdl model, you need define the formal component prototype
into a package, or into the architecture_declarative_part.

After this is a problem of instantiation.

Do a compilation/synthesis (as verilog netlist) of your vhdl part, do
the same with the verilog file; and now you have no more problem to mix
them.

If you only want do simulation. You can use Modelsim, that offer you
capability to mix the both code.

During instantiation (from the verilog point of view), you use the
first found model of the component that you have into the defined
working library.
The problem is that lot of tools haven't the same 'structure' to handle
vhdl and verilog model; and the 'structures' aren't easilly mixable.
But if you can esthablish a same format netlist for the both component,
generally you can mix them easilly.

JaI

 

[Jonathan Bromley]

anybody hate verilog

Janick Bergeron memorably wrote that he uses both VHDL and
Verilog, and at any given time he prefers whichever he's
not using at that time. I reckon that's not a bad summary.

Of course, when we have SystemVerilog 3.1a, which includes
everything that you could possibly want from VHDL, C++, PSL,
Vera, e and just about every other language you've ever
thought of, then we can use SystemVerilog for everything.
Presumably that means we will be able to dislike it
all the time.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Eric Smith]

Of course, when we have SystemVerilog 3.1a, which includes
everything that you could possibly want from VHDL, C++, PSL,
Vera, e and just about every other language you've ever
thought of, then we can use SystemVerilog for everything.
Presumably that means we will be able to dislike it
all the time.

So SystemVerilog is the PL/I of HDLs?