Mixed VHDL and Verilog question

Discussion in 'VHDL' started by marcoa.castellon@gmail.com, Dec 19, 2007.

  1. Guest

    Hello everyone.

    Would someone please provide an answer to the following "simple"
    question?

    How do you override the default value of the parameters of a Verilog
    module when you instantiate such a module in a VHDL top-level entity
    or testbench?

    Would the use of "generic map" work?

    Thank you.
    Marco
     
    , Dec 19, 2007
    #1
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  2. wrote:

    > How do you override the default value of the parameters of a Verilog
    > module when you instantiate such a module in a VHDL top-level entity
    > or testbench?


    With a text editor.

    > Would the use of "generic map" work?


    I can't imagine how.

    -- Mike Treseler
     
    Mike Treseler, Dec 19, 2007
    #2
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  3. > Would someone please provide an answer to the following "simple"
    > question?

    Simple question -> complex ansewer.

    > Would the use of "generic map" work?

    It will depend on the tools. All of the EDA SW I test, will correctly pass
    a vhdl generic mapping to a verilog parameter. If it doesn't the tool has
    a bug. Some tools will even support generaic maping inside of a
    configuration statement to overide verilog parameters. My best advice is
    try it with your software. If it doesn't work file a bug. They may come
    back and give you a work around.
     
    Dwayne Dilbeck, Dec 19, 2007
    #3
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