mixing in and out in the declaration of a port

Discussion in 'VHDL' started by cvt, Jul 9, 2008.

  1. cvt

    cvt

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    Hallo everyone

    I do not have a good VHDL reference manual yet so I need to post this simple question.

    I want to declare a 32 bit port AD where bits 0 to 3 and bit 19 are outputs and the rest are inputs. Keep in mind that in my (User Constraints File .ucf) I have done the pin mapping separately for each pin. Example:

    NET "AD<1>" LOC = "P199";
    .
    .
    NET "AD<31>" LOC = "P65" ;

    So what will the declaration look like.

    c
     
    cvt, Jul 9, 2008
    #1
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